MPC852T datasheet(78/80 Pages) FREESCALE

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MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Document Revision History

17 Document Revision History

Table 32 lists significant changes between revisions of this document.

Table 32. Document Revision History

Revision

Date

Changes

3.1

1/18/2005

Document template update.

3.0

11/2004

• Added sentence to Spec B1A about EXTCLK and CLKOUT being in

Alignment for Integer Values

• Added a footnote to Spec 41 specifying that EDM = 1

• Broke the Section 16.1, “Pin Assignments,” into 2 smaller sections

for the JEDEC and non-JEDEC pinouts.

2.0

12/2003

Put 852T on the 1st page in place of 8245.

Figure 62 on page 59 had overbars added on signals CR (pin G2) and

WAIT_A (pin P4).

1.8

7/2003

Changed the pinout to be JEDEC Compliant, changed timing

parameters B28a through B28d, and B29d to show that TRLX can be 0

or 1.

1.7

5/2003

Changed the SPI Master Timing Specs. 162 and 164

1.6

4/2003

Changed the package drawing in Figure 15-63

1.5

4/2003

Changed 5 Port C pins with interrupt capability to 7 Port C pins. Added

the Note: solder sphere composition for MPC852TVR and

MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure 15-63

1.4

2/2003

Changed Table 15-30 Pin Assignments for the PLL Pins VSSSYN1,

VSSSYN, VDDSYN

1.3

1/2003

Added subscripts to timing diagrams for B1-B35, to specify memory

controller settings for the specific edges.

1.2

1/2003

In Table 15-30, specified EXTCLK as 3.3 V.

1.1

12/2002

Added fast Ethernet controller to the features

11/2002

Added values for 80 and 100 MHz

10/2002

Initial release

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