CS4364 datasheet(42/50 Pages) CIRRUS

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DS619A1

CS4364

5.12

Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h)

These six registers provide individual volume and mute control for each of the six channels.

The values for “xx” in the bit fields above are as follows:

5.12.1

Digital Volume Control (xx_VOL7:0)

Default = 00h (0 dB)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments

from 0 to -127.5 dB. Volume settings are decoded as shown in Table 10. The volume changes are imple-

mented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that

the values in the volume setting column in Table 10 are approximate. The actual attenuation is determined

by taking the decimal value of the volume register and multiplying by 6.02/12.

5.13

PCM Clock Mode (address 16h)

5.13.1

Master Clock Divide by 2 Enable (MCLKDIV)

Function:

When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2

prior to all other internal circuitry.

When set to 0 (default), MCLK is unchanged.

543

xx_VOL7

xx_VOL6

xx_VOL5

xx_VOL4

xx_VOL3

xx_VOL2

xx_VOL1

xx_VOL0

000

Binary Code

Decimal Value

Volume Setting

00000000

0 dB

00000001

-0.5 dB

00000110

-3.0 dB

11111111

255

-127.5 dB

Table 10. Example Digital Volume Settings

543

Reserved

MCLKDIV

Reserved

000

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