CS4364 datasheet(26/50 Pages) CIRRUS

26 / 50 page

DS619A1

CS4364

3.8

Direct Stream Digital (DSD) Mode

In software mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode. The DSD_DIF bits

(Reg 04h) then control the expected DSD rate and MCLK ratio.

The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The first

method uses a decimation free DSD processing technique which allows for features such as matched PCM level

output, DSD volume control, and 50kHz on chip filter. The second method sends the DSD data directly to the on-

chip switched-capacitor filter for conversion (without the above mentioned features).

The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data input. In

this mode the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see

Figure 20). Use of phase modulation mode may not directly effect the performance of the CS4364, but may lower

the sensitivity to board level routing of the DSD data signals.

The CS4364 can detect errors in the DSD data which does not comply with the SACD specification. The

STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4364 to alter the incoming invalid DSD data.

Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the MUTEC pins

would be set according to the DAMUTE bit (Reg. 08h)).

More information for any of these register bits can be found in the “Parameter Definitions” on page 47.

The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index)

at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however, performance at

these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital volume control should be

set to -3.0 dB. This same volume control register affects PCM output levels. There is no need to change the vol-

ume control setting between PCM and DSD in order to have the 0 dB output levels match (both 0 dBFS and 0 dB-

SACD will output at -3 dB in this case).

Figure 20. DSD Phase Modulation Mode Diagram

BCKA

(128Fs)

BCKD

(64Fs)

DSD_SCLK

DSDAx,

DSDBx

DSD_SCLK

DSDAx,

DSDBx

BCKA

(64Fs)

DSD_SCLK

DSD Phase

Modulation Mode

DSD Normal Mode

Not Used

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