| поискавой системы для электроныых деталей |
|
CS4364 датащи(PDF) 20 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS4364 датащи(HTML) 20 Page - Cirrus Logic |
|
20 / 50 page ![]() 20 DS619A1 CS4364 3. APPLICATIONS The CS4364 serially accepts twos complement formatted PCM data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces see AN282 “The 2-Channel Serial Audio Interface: A Tutorial”. The CS4364 can be configured in hardware mode by the M0, M1, M2, M3 and M4 pins and in software mode through I²C or SPI. 3.1 Master Clock MCLK/LRCK must be an integer ratio as shown in Tables 1 - 3. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are then set to generate the proper internal clocks. Tables 1 - 3 illustrate several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous. Sample Rate (kHz) MCLK (MHz) 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 Table 1. Single-Speed Mode Standard Frequencies Sample Rate (kHz) MCLK (MHz) 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 Table 2. Double-Speed Mode Standard Frequencies Sample Rate (kHz) MCLK (MHz) 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 Table 3. Quad-Speed Mode Standard Frequencies = Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-mode detection. Please see “Switching Characteristics - PCM” on page 14. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |