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WM8771

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PP Rev 2.0 December 2001

33

REGISTER MAP

The complete register map is shown below. The detailed description can be found in the relevant text of the device description.

These can be controlled using the Control Interface. All unused bits should be set to ‘0’.

REGISTER

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

DEFAULT

R9(09h)

0

0

0

1

0

0

1

UPDATE

LDA1[7:0]

X11111111

R10(0Ah)

0

0

0

1

0

1

0

UPDATE

RDA1[7:0]

X11111111

R11(0Bh)

0

0

0

1

0

1

1

UPDATE

LDA2[7:0]

X11111111

R12(0Ch)

0

0

0

1

1

0

0

UPDATE

RDA2[7:0]

X11111111

R13(0Dh)

0

0

0

1

1

0

1

UPDATE

LDA3[7:0]

X11111111

R14(0Eh)

0

0

0

1

1

1

0

UPDATE

RDA3[7:0]

X11111111

R15(0Fh)

0

0

0

1

1

1

1

UPDATE

LDA4[7:0]

X11111111

R16(10h)

0

0

1

0

0

0

0

UPDATE

RDA4[7:0]

X11111111

R17(11h)

0

0

1

0

0

0

1

UPDATE

MASTDA[7:0]

X11111111

R18(12h)

0

0

1

0

0

1

0

0

PHASE[8:0]

000000000

R19(13h)

0

0

1

0

0

1

1

0

PL[3:0]

0

IZD

ATC

DZCEN

010010000

R20(14h)

0

0

1

0

1

0

0

0

RECMUTE[2:0]

MUTEALL

DMUTE[3:0]

000000000

R21(15h)

0

0

1

0

1

0

1

0

DZFM[3:0]

DEEMP[3:0]

000000000

R22(16h)

0

0

1

0

1

1

0

ADCHPD

0

0

WL[1:0]

BCP

LRP

FMT[1:0]

000100010

R23(17h)

0

0

1

0

1

1

1

MS

0

DACRATE[2:0]

ADCOSR

ADCRATE[2:0]

000010010

R24(18h)

0

0

1

1

0

0

0

0

0

0

DACD[3:0]

ADCD

PWDN

000111110

R25(19h)

0

0

1

1

0

0

1

0

0

LRBOTH

MUTE

LAG

000001100

R26(1Ah)

0

0

1

1

0

1

0

0

0

LRBOTH

MUTE

RAG

000001100

R27(1Bh)

0

0

1

1

0

1

1

AINPD

0

RMX

0

LMX

100000000

R28(1Ch)

0

0

1

1

1

0

0

OUTPD[1:0]

0

0

0

0

0

0

0

110000000

R29i1Dh)

0

0

1

1

1

0

1

OUTPD[3:2]

0

0

0

0

0

0

0

110000000

R31(1Fh)

0

0

1

1

1

1

1

RESET

Not reset

ADDRESS

DATA

DEFAULT