WM8771 datasheet(23/44 Pages) WOLFSON

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WM8771

PP Rev 2.0 December 2001

D14

D15

Figure 20 CCB Interface – CL stopped high

A[7:0] are Device Address bits

D[15:9] are Control Address bits

D[8:0] are Control Data bits

The address A[7:0] for WM8771 is 8Ch (10001100).

CONTROL INTERFACE REGISTERS

DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits:

BIT

LABEL

DEFAULT

DESCRIPTION

10110

Interface Control

1:0

FMT[1:0]

Interface format Select

00 : right justified mode

01: left justified mode

10: I2S mode

11: DSP (early or late) mode

In left justified, right justified or I2S modes, the LRP register bit controls the polarity of

ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the

opposite of that shown Figure 11, Figure 12 and Figure 13. Note that if this feature is used as a

means of swapping the left and right channels, a 1 sample phase difference will be introduced. In

DSP modes, the LRP register bit is used to select between early and late modes.

BIT

LABEL

DEFAULT

DESCRIPTION

In left/right/i2s modes:

ADCLRC/DACLRC Polarity (normal)

0 : normal ADCLRC/DACLRC

polarity

1: inverted ADCLRC/DACLRC

polarity

10110

Interface Control

LRP

In DSP mode:

0 : Early DSP mode

1: Late DSP mode

By default, ADCLRC/DACLRC and DIN1/2/3/4 are sampled on the rising edge of BCLK and should

ideally change on the falling edge. Data sources that change ADCLRC/DACLRC and DIN1/2/3/4 on

the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts

the polarity of BCLK to the inverse of that shown in Figure 11, Figure 12, Figure 13, Figure 14,

Figure 15, Figure 16 and Figure 17.

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