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WM8771 датащи(PDF) 20 Page - Wolfson Microelectronics plc |
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WM8771 датащи(HTML) 20 Page - Wolfson Microelectronics plc |
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20 / 44 page ![]() WM8771 Product Preview w PP Rev 2.0 December 2001 20 ADCLRC BCK DOUT Input Word Length (IWL) 1/fs LEFT CHANNEL n 2 1 n-1 LSB MSB n 2 1 n-1 RIGHT CHANNEL NO VALID DATA 1 BCLK 1 BCLK DSP EARLY MODE In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8771 on the second rising edge on BCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data follow DAC channel 1 left data (Figure 14). DACLRC BCK DIN1 Input Word Length (IWL) 1/fs CHANNEL 1 LEFT n 2 1 n-1 LSB MSB n 2 1 n-1 CHANNEL 1 RIGHT 2 1 CHANNEL 2 LEFT n n-1 CHANNEL 4 RIGHT NO VALID DATA 1 BCLK 1 BCLK Figure 14 DSP Early Mode Timing Diagram – DAC data input The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 15) Figure 15 DSP Early Mode Timing Diagram – ADC data output |
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