SST49LF080A datasheet(15/49 Pages) SST

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Data Sheet

8 Mbit LPC Flash

SST49LF080A

S71235-00-000

4/03

Multiple Device Selection

Multiple LPC flash devices may be strapped to increase

memory densities in a system. The four ID pins, ID[3:0],

allow up to 16 devices to be attached to the same bus by

using different ID strapping in a system. BIOS support, bus

loading, or the attaching bridge may limit this number. The

boot device must have an ID of 0 (determined by ID[3:0]);

subsequent devices use incremental numbering. Equal

density must be used with multiple devices.

When used as a boot device, ID[3:0] must be strapped as

0000; all subsequent devices should use a sequential up-

count strapping (i.e. 0001, 0010, 0011, etc.). With the hard-

ware strapping, ID information is included in every LPC

address memory cycle. The ID bits in the address field are

inverse of the hardware strapping. The address bits

[A24:A23, A21:A20] are used to select the device with proper

IDs. See Table 7 for IDs. The SST49LF080A will compare

these bits with ID[3:0]’s strapping values. If there is a mis-

match, the device will ignore the remainder of the cycle.

Registers

There are two registers available on the SST49LF080A,

the General Purpose Inputs Registers (GPI_REG) and the

JEDEC ID Registers. Since multiple LPC memory devices

may be used to increase memory densities, these registers

appear at its respective address location in the 4 GByte

system memory map. Unused register locations will read

as 00H. Any attempt to read registers during internal Write

operation will respond as “Write operation status detection”

(Data# Polling or Toggle Bit). Any attempt to write any reg-

isters during internal Write operation will be ignored. Table

9 lists GPI_REG and JEDEC ID address locations for

SST49LF080A with its respective device strapping.

TABLE

7: MULTIPLE DEVICE SELECTION

CONFIGURATION

Device #

Hardware

Strapping

Address Bits Decoding

ID[3:0]

A24

A23

A21

A20

0 (Boot device)

0000

1111

0001

1110

0010

1101

0011

1100

0100

1011

0101

1010

0110

1001

0111

1000

0111

1001

0110

1010

0101

1011

0100

1100

0011

1101

0010

1110

0001

1111

0000

T7.0 1235

TABLE

8: GENERAL PURPOSE INPUTS REGISTER

Bit

Function

Pin #

32-PLCC

32-TSOP

7:5

Reserved

4GPI[4]

Reads status of general

purpose input pin

3GPI[3]

Reads status of general

purpose input pin

311

2GPI[2]

Reads status of general

purpose input pin

412

1GPI[1]

Reads status of general

purpose input pin

513

0GPI[0]

Reads status of general

purpose input pin

614

T8.0 1235

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