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SST49LF080A датащи(PDF) 17 Page - Silicon Storage Technology, Inc |
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SST49LF080A датащи(HTML) 17 Page - Silicon Storage Technology, Inc |
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17 / 49 page ![]() Data Sheet 8 Mbit LPC Flash SST49LF080A 17 ©2003 Silicon Storage Technology, Inc. S71235-00-000 4/03 PARALLEL PROGRAMMING MODE Device Operation Commands are used to initiate the memory operation func- tions of the device. The data portion of the software com- mand sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#. Reset Driving the RST# low will initiate a hardware reset of the SST49LF080A. See Table 23 for Reset timing parameters and Figure 16 for Reset timing diagram. Read The Read operation of the SST49LF080A device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- ing diagram, Figure 17, for further details. Byte-Program Operation The SST49LF080A device is programmed on a byte-by- byte basis. Before programming, one must ensure that the sector in which the byte is programmed is fully erased. The Byte-Program operation is initiated by executing a four-byte command load sequence for Software Data Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation, the row address (A10-A0) is latched on the falling edge of R/C# and the column address (A21-A11) is latched on the rising edge of R/C#. The data bus is latched on the rising edge of WE#. The Program operation, once initiated, will be completed, within 20 µs. See Figure 21 for Program operation timing diagram and Figure 33 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. Dur- ing the internal Program operation, the host is free to per- form additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector archi- tecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 22 for Sector-Erase timing wave- forms. Any commands written during the Sector-Erase operation will be ignored. Block-Erase Operation The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for the SST49LF080A. The Block-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Block-Erase command (50H) and block address. The internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be deter- mined using either Data# Polling or Toggle Bit methods. See Figure 23 for Block-Erase timing waveforms. Any com- mands written during the Block-Erase operation will be ignored. Chip-Erase Operation The SST49LF080A devices provide a Chip-Erase opera- tion, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 11 for the command sequence, Figure 24 for Chip-Erase timing diagram, and Figure 36 for the flowchart. Any commands written during the Chip-Erase operation will be ignored. |
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