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SST49LF080A датащи(PDF) 33 Page - Silicon Storage Technology, Inc

номер детали SST49LF080A
подробное описание детали  8 Mbit LPC Flash
PDF  49 Pages
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производитель  SST [Silicon Storage Technology, Inc]
домашняя страница  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST49LF080A датащи(HTML) 33 Page - Silicon Storage Technology, Inc

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Data Sheet
8 Mbit LPC Flash
SST49LF080A
33
©2003 Silicon Storage Technology, Inc.
S71235-00-000
4/03
TABLE 21: READ CYCLE TIMING PARAMETERS, VDD=3.0-3.6V (PP MODE)
Symbol
Parameter
Min
Max
Units
TRC
Read Cycle Time
270
ns
TRST
RST# High to Row Address Setup
1
µs
TAS
R/C# Address Set-up Time
45
ns
TAH
R/C# Address Hold Time
45
ns
TAA
Address Access Time
120
ns
TOE
Output Enable Access Time
60
ns
TOLZ
OE# Low to Active Output
0
ns
TOHZ
OE# High to High-Z Output
35
ns
TOH
Output Hold from Address Change
0
ns
T21.0 1235
TABLE 22: PROGRAM/ERASE CYCLE TIMING PARAMETERS, VDD=3.0-3.6V (PP MODE)
Symbol
Parameter
Min
Max
Units
TRST
RST# High to Row Address Setup
1
µs
TAS
R/C# Address Setup Time
50
ns
TAH
R/C# Address Hold Time
50
ns
TCWH
R/C# to Write Enable High Time
50
ns
TOES
OE# High Setup Time
20
ns
TOEH
OE# High Hold Time
20
ns
TOEP
OE# to Data# Polling Delay
40
ns
TOET
OE# to Toggle Bit Delay
40
ns
TWP
WE# Pulse Width
100
ns
TWPH
WE# Pulse Width High
100
ns
TDS
Data Setup Time
50
ns
TDH
Data Hold Time
5
ns
TIDA
Software ID Access and Exit Time
150
ns
TBP
Byte Programming Time
20
µs
TSE
Sector-Erase Time
25
ms
TBE
Block-Erase Time
25
ms
TSCE
Chip-Erase Time
100
ms
T22.0 1235
TABLE 23: RESET TIMING PARAMETERS, VDD=3.0-3.6V (PP MODE)
Symbol
Parameter
Min
Max
Units
TPRST
VDD stable to Reset Low
1
ms
TRSTP
RST# Pulse Width
100
ns
TRSTF
RST# Low to Output Float
48
ns
TRST1
1. There may be additional reset latency due to TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation.
RST# High to Row Address Setup
1
µs
TRSTE
RST# Low to reset during Sector-/Block-Erase or Program
10
µs
TRSTC
RST# Low to reset during Chip-Erase
50
µs
T23.0 1235



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