GD9FS1G6F2AMG datasheet(26/55 Pages) GIGADEVICE

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GD9Fx1GxF2A

8.3 Block Erase Operation (60H-D0H)

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase

Setup command (60H). Only address Row Address is valid while Column Addresses ignored. The Erase Confirm

command (D0H) following the block address loading initiates the internal erasing process. At the rising edge of WE after

the erase confirm command input, the internal write controller handles erase and erase verify. Once the erase process

starts, the Read Status Register command may be entered to read the status register. The system controller can detect

the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read

Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the

Write Status Bit (I/O 0) may be checked.

60H

Address

(2cycle)

D0H

70H

Status

tBERS

R/B#

I/Ox

Row Add 1.2

Figure 22: Common Block Erase Operation figures

8.4 Reset (FFH)

The device offers a reset feature, executed by writing FFH to the command register. When the device is in busy state

during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells

being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to

wait for the next command, and the Status Register is cleared to value C0h when R/B# is high. If the device is already in

reset state a new reset command will be accepted by the command register. The R/B# pin transitions to low for tRST after

the Reset command is written.

FFH

tRST

tWB

CE#

CLE

WE#

I/Ox

R/B#

Figure 23: Reset (FFH) figures

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