M65818AFP

Rev.1.00, Sep.04.2003, page 33 of 38

• Reverse Lch/Rch for PWM Output pins(bit9: CHSEL).

"L": Lch/Rch no reverse, "H": Lch/Rch reverse.

• ∆Σ: Rch Input Phase (bit10: DRPOL).

"L"…. Same phase ("Through")

"H"…..This setting makes

∆Σ Rch Input in reverse, further makes PWM block input phase reverse, ultimately

phase becomes positive phase ( Input pin and Output pin's phase is same).

• Sampling Rate Converter Block Reset (Initialize function) (bit11: SRCRST).

"L" …..normal operation

"H" to "L" edge…..Reset ( Initialize function)

• Zero Mute of Gain Control Input (bit13: GIMUTE).

"L"…Mute release, "H"…Mute.

• Duty 50% Mute of PWM Output (bit14: NSPMUTE).

Fixed PWM duty 50% Mute

"L"…..Mute release

"H"….. Mute

This function exists also in a pin by the same name.(This Mute function can be set either NSPMUTE flag or

NSPMUTE pin.)

• G-Mute for PWM Output Data (bit15: PGMUTE)

At G-MUTE flag = H , PGMUTE pin fixes each PWM Output as followings.

"L"….. Mute release "H"….. Fixed Mute for PWM Output (Fixed value as follows)

<Serial Control (System1 Mode :bit24) PWMHP="L" >

OUTL1(+) and OUTR1(+) ="L" , OUTL2(+) and OUTR2(+) = "L"

OUTL1(-) and OUTR1(-) ="H" , OUTL2(-) and OUTR2(-) = "H"

<Serial control (system1 mode; bit24) PWMHP="H">

OUTL1(+) and OUTR1(+) ="L" , OUTL2(+) and OUTR2(+) = "L"

OUTL1(-) and OUTR1(-) ="L" , OUTL2(-) and OUTR2(-) = "H"

This function exists also in a pin by the same name.(This Mute function can be set either PGMUTE flag or

PGMUTE pin.)

• ∆ΣBlock : operating rate (bit16: NSSPEED).

Refer to Table 6-3-4.

"L"…16fso

"H"…32fso *Enable only MCKSEL="L"(1024fso), NSOBIT="H" only.

(Except for this condition, Operating rate automatically becomes 16fso.)

• ∆Σ Block : The setting of bit length (bit17: NSOBIT).

Refer to Table 6-3-4.

NSOBIT selects bit length for

∆Σ operation. This is set by force as 5bit at MCKSEL="H".

"L"…6bit (63 value)

"H"…5bit (31value)

• ∆ΣBlock: DC dithering Rch Phase (bit18: DCDRPOL).

"L"…Same phase

"H"…Reverse phase

• ∆Σ Block: DC dithering Selection (bit19,bit20: DCDSEL0,DCDSEL1).

Refer to Table 6-3-2.