M65818AFP datasheet(31/39 Pages) RENESAS

31 / 39 page

M65818AFP

Rev.1.00, Sep.04.2003, page 31 of 38

*NOTE2; Selection of PWM output form

Pay attention in selection and setting above-mentioned that a noise may occur by internal clock changes when setting of

MCKSEL pin is changed and the serial control System2 mode:

bit17 (NSOBIT) and bit16 (NSSPEED).

Since especially MCKSEL pin sets up an internal master clock, use with a fixed value recommended.

In changing MCKSEL, initialization with INIT pin and a re-setup of all the bits by serial control are needed after

changing MCKCEL.

• Reverse Phase of PWM Output OUTL1(-) / OUTR1(-) (bit24:PWMHP)

"L"…PWM Output OUTL1(-) / OUTR1(-) are reverse phase as the PWM output OUTL1(+) / OUTR1(+) .

"H"…PWM Output OUTL1(-) / OUTR1(-) are same phase as the PWM output OUTL1(+) / OUTR1(+) .

In this mode, the signal which added OUTL1(-) / OUTR1(-) and OUTL2(-) / R2(-) by external resistance can be

given to LPF / Headphone Amplifier.

6.3. System2 Mode (Secondary side)

bit

Flag Name

Functional Explanation

INIT

MODE1

Mode Setting 1

"H" fixed



MODE2

Mode Setting 2

"L" fixed



IMCKSEL

Input Master Clock Selection

512fsi

256fsi

DSDFCO0

Refer to Table 6-3-1.

5DSDFCO1

Filter Coefficient of Down

Sampling

SYNC

Resynchronization

L->H :

Resynchronization.

XFsoOEN

XfsoOUT pin output "enable"

disable

enable

ASYNCEN2

Asynchronous Detection Flag for

secondary Side

enable

disable

CHSEL

L / R inversion of PWM

output

Active

Non-active

DRPOL

∆ΣBlock: Rch Input Phase

Negative-phase

Positive-phase

SRCRST

Sampling Rate Converter

Reset

Active

Non-active

don't care



GIMUTE

Zero Mute at Gain Control

Input Clock

Active

Non-active

NSPMUTE

Duty 50 percent Mute of

PWM Output

Active

Non-active

PGMUTE

G_MUTE of PWM Output

Data

Active

Non-active

NSSPEED

∆Σ Block: Operation Speed

32fso

16fso

NSOBIT

∆Σ Block: Setting of Output

Bit Number

5 bits (31 value)

6 bits (63 value)

DCDRPOL

∆Σ Block: Rch Phase of DC

dithering

Negative-phase

Positive-phase

DCDSEL0

Refer to Table 6-3-2

DSDSEL1

∆ΣBlock: DC dithering

Selection

ACDRPOL

∆Σ Block: Rch Phase of AC

dithering

Negative-phase

Positive-phase

ACDSEL0

Refer to Table 6-3-3

ACDSEL1

ACDSEL2

∆Σ Block: AC dithering

selection

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