M65818AFP

Rev.1.00, Sep.04.2003, page 17 of 38

<Single use>

The primary side: M65818AFP synchronizes with EXWCK (internal 8 dividing clock).

Thereby it synchronize with an input device.

The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is

connected to FsoI, In other way,

By setting secondary side asynchronous detection to "disable" with "ASYNCEN2" flag(Serial Control,System2

mode,bit8), FsoI can also be considered as fixation.

In this mode, M65818AFP always perform synchronous detection between EXWCK pin's clock in primary side.

Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous

detection perform as ` forced-enable`.

• External 8fs Data Mode (The case of secondary side synchronization)

<Multiplex use and Single use> (common)

The primary side: Synchronous operation does not carry out since internal sampling rate converter is not used.

In this mode, asynchronous detection by the primary side is set to disable by force.

Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous

detection perform as ` forced-disable`.

The Secondary Side: M65818AFP synchronizes with FsoCKO of Master IC (in single use, it is own IC).

One of the M65818AFP becomes a master, and the synchronization between ICs is carried out by FsoCKO of

Master IC.FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.

Moreover, the rise edge of FsoCKO sent from M65818AFP and the rise edge of EXWCK (8fs) which comes from

the external device need to be with a synchronous phase.

• SACD-fsi Mode

<Multiplex use>

The primary side: M65818AFP synchronizes with FsiI inputted in common to each IC. And primary side

synchronous DSD128Fs/DSD64Fs are used as a clock in common to all ICs.

Thus, DSD128 Fs/DSD64Fs in common to all ICs is inputted (all IC DSDCKIO=L) or the DSD128 Fs/DSD64Fs

output (DSDCKIO="H") generated by dividing of the primary side master clock within Master IC is inputted Into

the DSD128 Fs/DSD64Fs (DSDCKIO="L") of other slaves IC. The synchronous operation of the SACD input in

the case of multi is possible by doing in this way.

The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master

IC, and the synchronization between ICs is carried out by FsoCKO of Master IC.

FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.

<Single use>

The primary side: Input to FsiI pin or set FsiI as fixed by setting primary side asynchronous detection to disable by

serial control "System1 mode:bit16 (ASYNCEN1)".

The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is

connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2"

flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation.