M65818AFP

Rev.1.00, Sep.04.2003, page 15 of 38

5.7. XfsiIN

64

XfsiIN pin is primary master clock input.

Frequency of primary master clock must be selected by the serial control "System2 mode:bit3".

bit3(IMCKSEL)

XfsiIN

H

512fsi

L

256fsi

• The relations between input signal sampling rate and master clock frequency.

Input sampling rate

Primary clock 512fsi/256fsi[Hz]

Secondary clock 1024fso/512fso[Hz]

1fsi: 32k / 2fsi: 64k / 4fsi: 128k

16.384M/8.192M

32.768M/16.384M

1fsi: 44.1k / 2fsi: 88.2k / 4fsi: 176.4k

22.579M/11.290M

1fsi: 48k / 2fsi: 96k / 4fsi: 192k

24.576M/12.288M

49.152M/24.576M

Input signal and primary clock are related to synchronization. The primary clock frequency are 512 or 256 times as

much as the input signal fsi ( 32k, 44.1k and 48k.)

The primary and secondary clock are related to independence. ( asynchronization )

At 1024fso setting, secondary clock= frequency range from 32.768MHz to 49.152MHz.

At 512fso setting, secondary clock = frequency range from 16.384MHz to 24.576MHz.

5.8. CKCTL1, CKCTL2, CKOUT1, CKOUT2, CKOUT3

56 57 65 66 67

CKOUT1, CKOUT2, and CKOUT3 pins are divided-clock output from secondary clock.

At power on, these frequency is free-running.

The states of CKCTL1 and CKCTL2 pins selects clock frequency of CKOUT1,CKOUT2,and CKOUT3 pins.

The setting table of CKCTL1 and CKCTL2 pins is shown below.

CKCTL1

CKCTL2

CKOUT1

CKOUT2

CKOUT3

L

L

LLL

L

H

256Fso

16Fso

8Fso

H

L

512Fso

256Fso

16Fso

H

H

512Fso

256Fso

8Fso

5.9. FsoCKO

73

FsoCKO is clock output pin of 1fso frequency. The output is divided-clock of XfsoIN, and frequency is free-running

at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used plural M65818AFP,take a

synchronization between M65818AFP and other external devices.

Detail explanation is shown in next paragraph, "SYNC".

5.10. SYNC, FsoI, FsiI, SFLAG

42 74 46 72

M65818AFP synchronizes in clock input from the external source devices. So it makes synchronized operation between

source devices or another M65818AFP ( in case of Multi channel Operation )

The clock which can be set as the object of an synchronization is a clock of FsoI (1fso), FsiI (1fsi), LRCK (1/2/4 fsi),

and EXWCK (8fs). The object clock changes by input signal mode setting.

These relations are shown in following table.