M65818AFP

Rev.1.00, Sep.04.2003, page 32 of 38

Table 6-3-1 Setting of Down Sampling Filter Coefficient

bit

Flag Name

ROM1

ROM2

ROM3

ROM4

4DSDFCO0

LH

LH

5DSDFCO1

LL

H

H

Table 6-3-2 DC dithering Selection at

∆Σ

∆Σ

∆Σ

∆Σ Block

bit

Flag Name

Non-dithering

DC dithering

0.1%

DC dithering

0.2%

DC dithering0.4%

19

DCDSEL0

L

H

L

H

20

DCDSEL1

L

L

H

H

Table 6-3-3 AC dithering Selection at

∆Σ

∆Σ

∆Σ

∆Σ Block

bit

Flag Name

Non-dithering

AC dithering A

AC dithering C

AC dithering E

22

ACDSEL0

don't care

L

L

L

23

ACDSEL1

L

H

L

H

24

ACDSEL2

L

L

H

H

Table 6-3-4 Setup Operating Rate & Bit Length of

∆Σ

∆Σ

∆Σ

∆Σ Block

bit

Flag / Pin

Name

16fso,6bit

16fso,5bit

16fso,5bit

32fso,5bit

16

NSSPEED

L

L

X

H

17

NSOBIT

L

H

X

H

pin

MCKSEL

L(Secondary

Clock1024fso)

L(Secondary

Clock1024fso)

L(Secondary

Clock512fso)

L(Secondary

Clock1024fso)

• Input Master Clock Selection (bit3:IMCKSEL).

"L":256fsi

"H":512fsi ("512fsi" are divided into half "256fsi" and operate as primary master clock.)

• Selection of Down Sampling Filter Coefficient for SACD input (bi4, bit5: DSFCO 0,DSFCO 1).

Refer to Table 6-3-1.

• Resynchronization (bit6: SYNC).

Resynchronization function is same at SYNC pin's function. Refer to Operation Explanation, Chapter 5.10.

Resynchronization process starts by SYNC rise edge,

therefore SYNC level must be fixed to "L" just before SYNC operation.

• "Enable" of XfsoOUT pin Output(bit7: XfsoOEN).

"L": Clock Output (enable), "H": L fixed (disable)

• Flag to "Enable" Asynchronous Detection for Secondary Block (bit8: ASYNCEN2).

ASYNCEN2 : "L"…disable.

"H"…enable.

Under condition of ASYNCEN2="L", secondary side asynchronous detection is in-effective under asynchronous

position, whether Fsol Clock is not inputted, there by M65818AFP does not operate function for instance mute

operation.