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DM562AP
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
28
Preliminary
Version: DM562AP-DS-P02
March 05, 2004
Revision ID (xxxxxx08 - PCIRV)
31
0
7
8
Revision ID
Class Code
3
4
Class Code
Revision Major Number
Revision Minor Number
Bit
Default
Type
Description
31:8
070002h
RO
Class Code (070002h)
This is the standard code for Simple Communications controller.16550
compatible serial controler.
7:4
0001
RO
Revision Major Number
This is the silicon-major revision number that will increase for the
subsequent versions of the DM6588A
3:0
0000
RO
Revision Minor Number
This is the silicon-minor revision number that will increase for the
subsequent versions of the DM6588A.
Miscellaneous Function (Xxxxxx0c - PCILT)
31
16 15
0
87
23
24
BIST
Header Type
Latency Timer
Cache Line Size
Built-In Self Test
Header Type
Latency Timer For The Bus Master
Cache Line Size For Memory Read
Bit
Default
Type
Description
31:24
00h
RO
Built-In Self Test (=00h Means No Implementation)
23:16
00h
RO
Header Type (= 00h Means single function with Predefined Header Type )
15:8
00h
RO
Latency Timer For The Bus Master.
The DM6588A will never support the function.
7:0
00h
RO
Cacheline Size For Memory Read Mode Selection (00h Means No
Implementation For Use)
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