DM562AP
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
26
Preliminary
Version: DM562AP-DS-P02
March 05, 2004
Bit
Default
Type
Description
31
0
R/C
Detected Parity Error
The DM6588A samples the AD[0:31], C/BE[0:3]#, and the PAR
signal to check parity and to set parity errors.
30
0
R/C
Signaled System Error
This bit is set when the SERR# signal is driven by the
DM6588A. This system error occurs when an address parity is
detected under the condition that bit 8 and bit 6 in command
register below are set.
29
0
R/C
Master Abort Detected
The DM6588A will never support the function
28
0
R/C
Target Abort Detected
The DM6588A will never support the function
27
0
RO
Send Target Abort (0 For No Implementation)
The DM6588A will never support the function.
26:25
10
RO
DEVSEL Timing (10 Select Slow Timing)
Slow timing of DEVSEL# means the DM6588A will assert
DEVSEL# signal two clocks after FRAME# is sample
“asserted.”
24
0
R/C
Data Parity Error Detected
The DM6588A will never support the function
23
0
RO
Slave mode Fast Back-To-Back Capable (1 For Good
Capability)
The DM6588A will never support the function
22
0
RO
User-Definable-Feature Supported
(0 For No Support)
21
0
RO
66 MHz Capable (0 For No Capability)
20
1
RO
_WR
New Capabilities
This bit indicates whether this function implements a list of
extended capabilities such as PCI power management. When
set this bit indicates the presence of New Capabilities. A value
of 0 means that this function does not implement New
Capabilities.
19:16
0000
RO
Reserved
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