AD9914SLASHPCBZ datasheet(41/45 Pages) AD

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Data Sheet

AD9914

Rev. F | Page 41 of 45

Bit(s)

Mnemonic

Description

DRG over output enable

0 = disables the DROVER output.

1 = enables the DROVER output.

Open

Open.

SYNC_CLK enable

0 = the SYNC_CLK pin is disabled and forced to a static Logic 0 state; the internal clock signal

continues to operate and provide timing to the data assembler.

1 = the internal SYNC_CLK signal appears at the SYNC_CLK pin (default).

SYNC_CLK invert

0 = normal SYNC_CLK polarity; Q data associated with Logic 1, I data with Logic 0 (default).

1 = inverted SYNC_CLK polarity.

Reserved

Keep logic 0.

[8:0]

Open

Open.

Control Function Register 3 (CFR3)—Address 0x02

Table 17. Bit Descriptions for CFR3

Bit(s)

Mnemonic

Description

[31:23]

Open

Open.

Input divider reset

0 = disables input divider reset function.

1 = initiates an input divider reset.

[21:20]

Input divider

Divides the input REF CLK signal by one of four values (1, 2, 4, 8). Bit 17 must be set to Logic 1

to enable the PLL input divider.

00 = divide by 1.

01 = divide by 2.

10 = divide by 4.

11 = divide by 8.

Doubler enable

0 = disables the doubler feature.

1 = enables the doubler feature. Must have the doubler clock edge bit set to Logic 1 to utilize

this feature.

PLL enable

0 = disables the internal PLL.

1 = the internal PLL is enabled and the output generates the system clock. The PLL must be

calibrated when enabled via VCO calibration in Register CFR1, Bit 24.

PLL input divider enable

0 = disables the PLL input divider function.

1 = enables the PLL input divider function.

Doubler clock edge

0 = disables the internal doubler circuit.

1 = enables the doubler circuit. Must have doubler enable bit set to Logic 1 to utilize this

feature.

[15:8]

Feedback divider N

The N divider value in Bits[15:8] is one part of the total PLL multiplication available. The second

part is the fixed divide by two element in the feedback path. Therefore, the total PLL

multiplication value is 2N. The valid N divider range is 10× to 255×. The default N value for

Bits[15:8] = 25. This sets the total default PLL multiplication to 50× or 2N.

Open

Open.

Manual ICP selection

0 = the internal charge pump current is chosen automatically during the VCO calibration

routine (default).

1 = the internal charge pump is set manually per Table 7.

[5:3]

ICP

Manual charge pump current selection. See Table 7.

Lock detect enable

0 = disables PLL lock detection.

1 = enables PLL lock detection.

[1:0]

Minimum LDW

Selects the number of REF CLK cycles that the phase error (at the PFD inputs) must remain

within before a PLL lock condition can be read back via Bit 24 in Register 0x00.

00 = 128 REF CLK cycles.

01 = 256 REF CLK cycles.

10 = 512 REF CLK cycles.

11 = 1024 REF CLK cycles.

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