AD9914SLASHPCBZ datasheet(4/45 Pages) AD

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AD9914

Data Sheet

Rev. F | Page 4 of 45

SPECIFICATIONS

DC SPECIFICATIONS

AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ,

IOUT = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

DVDD_I/O

3.135

3.30

3.465

Pin 16, Pin 83

DVDD

1.71

1.80

1.89

Pin 6, Pin 23, Pin 73

AVDD (3.3 V)

3.135

3.30

3.465

Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,

Pin 53, Pin 60

AVDD (1.8 V)

1.71

1.80

1.89

Pin 32, Pin 56, Pin 57

SUPPLY CURRENT

See also the total power dissipation specifications

IDVDD_I/O

Pin 16, Pin 83

IDVDD

433

Pin 6, Pin 23, Pin 73

IAVDD(3.3V)

640

Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,

Pin 53, Pin 60

IAVDD(1.8V)

178

Pin 32, Pin 56, Pin 57

TOTAL POWER DISSIPATION

Base DDS Power, PLL Disabled

2392

3091

3.5 GHz, single-tone mode, modules disabled, linear

sweep disabled, amplitude scaler disabled

Base DDS Power, PLL Enabled

2237

2627

2.5 GHz, single-tone mode, modules disabled, linear

sweep disabled, amplitude scaler disabled

Linear Sweep Additional Power

Modulus Additional Power

Amplitude Scaler Additional Power

138

Manual or automatic

Full Power-Down Mode

400

616

Using either the power-down and enable register or the

EXT_PWR_DWN pin

CMOS LOGIC INPUTS

Input High Voltage (VIH)

2.0

DVDD_I/O

Input Low Voltage (VIL)

0.8

Input Current (IINH, IINL)

±60

±200

µA

At VIN = 0 V and VIN = DVDD_I/O

Maximum Input Capacitance (CIN)

CMOS LOGIC OUTPUTS

Output High Voltage (VOH)

2.7

DVDD_I/O

IOH = 1 mA

Output Low Voltage (VOL)

0.4

IOL = 1 mA

REF CLK INPUT CHARACTERISTICS

REF CLK inputs must always be ac-coupled (both

single-ended and differential)

REF CLK Multiplier Bypassed

Input Capacitance

Single-ended, each pin

Input Resistance

1.4

kΩ

Differential

Internally Generated DC Bias

Voltage

Differential Input Voltage

0.8

1.5

V p-p

REF CLK Multiplier Enabled

Input Capacitance

Single-ended, each pin

Input Resistance

1.4

kΩ

Differential

Internally Generated DC Bias

Voltage

Differential Input Voltage

0.8

1.5

V p-p

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