AD9914SLASHPCBZ datasheet(31/45 Pages) AD

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Data Sheet

AD9914

Rev. F | Page 31 of 45

SERIAL PROGRAMMING

To enable SPI operations, set Pin 28 (F0) to logic high and Pin 29

to Pin 31 (F1 to F3) to logic low. To program the AD9914 with a

parallel interface, see the Parallel Programming section.

CONTROL INTERFACE—SERIAL INPUT/OUTPUT

The AD9914 serial port is a flexible, synchronous serial commu-

nications port allowing easy interface to many industry-standard

microcontrollers and microprocessors. The serial input/output is

compatible with most synchronous transfer formats.

The interface allows read/write access to all registers that configure

the AD9914. MSB-first or LSB-first transfer formats are supported.

In addition, the serial interface port can be configured as a single

pin input/output (SDIO) allowing a 2-wire interface, or it can be

configured as two unidirectional pins for input/output (SDIO

and SDO), enabling a 3-wire interface. Two optional pins

(I/O_SYNC and CS) enable greater flexibility for designing

systems with the AD9914.

Table 11. Serial Input/Output Pin Description

Pin No.

Mnemonic

Serial Input/Output Description

D4/SYNCIO

SYNCIO

D3/SDO

SDO

D2/SDIO/WR

SDIO

D1/SCLK/RD

SCLK

D0/CS/PWD

CS—chip select

GENERAL SERIAL INPUT/OUTPUT OPERATION

There are two phases to a serial communications cycle. The first

is the instruction phase to write the instruction byte into the

AD9914. The instruction byte contains the address of the register

to be accessed and defines whether the upcoming data transfer

is a write or read operation.

For a write cycle, Phase 2 represents the data transfer between

the serial port controller to the serial port buffer. The number

of bytes transferred is a function of the register being accessed.

For example, when accessing Control Function Register 2

(Address 0x01), Phase 2 requires that four bytes be transferred.

Each bit of data is registered on each corresponding rising edge

of SCLK. The serial port controller expects that all bytes of the

out of sequence for the next communication cycle. However,

one way to write fewer bytes than required is to use the SYNCIO

pin feature. The SYNCIO pin function can abort an input/output

operation and reset the pointer of the serial port controller.

After a SYNCIO, the next byte is the instruction byte. Note that

every completed byte written prior to a SYNCIO is preserved in

the serial port buffer. Partial bytes written are not preserved. At

the completion of any communication cycle, the AD9914 serial

port controller expects the next eight rising SCLK edges to be

the instruction byte for the next communication cycle.

After a write cycle, the programmed data resides in the serial

port buffer and is inactive. I/O_UPDATE transfers data from

the serial port buffer to active registers. The input/output

update can be sent either after each communication cycle or

when all serial operations are complete. In addition, a change in

profile pins can initiate an input/output update.

For a read cycle, Phase 2 is the same as the write cycle with the

following differences: data is read from the active registers, not

the serial port buffer, and data is driven out on the falling edge

of SCLK.

Note that, to read back any profile register (0x0B to 0x1A), the

three external profile pins must be used. For example, if the

profile register is Profile 5 (0x15), the PS[0:2] pins must equal

101.This is not required to write to the profile registers.

INSTRUCTION BYTE

The instruction byte contains the following information as

shown in the instruction byte information bit map.

Instruction Byte Information Bit Map

MSB

LSB

R/W

R/W—Bit 7 of the instruction byte determines whether a read

or write data transfer occurs after the instruction byte write.

Logic 1 indicates a read operation. Logic 0 indicates a write

operation.

X—Bit 6 of the instruction byte is don’t care.

A5, A4, A3, A2, A1, A0—Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0

of the instruction byte determine which register is accessed

during the data transfer portion of the communications cycle.

SERIAL INPUT/OUTPUT PORT PIN DESCRIPTIONS

SCLK—Serial Clock

The serial clock pin synchronizes data to and from the AD9914

and to run the internal state machines.

CS—Chip Select Bar

CS is an active low input that allows more than one device on

the same serial communications line. The SDO and SDIO pins

go to a high impedance state when this input is high. If driven

high during any communications cycle, that cycle is suspended

until CS is reactivated low. Chip select (CS) can be tied low in

systems that maintain control of SCLK.

SDIO—Serial Data Input/Output

Data is always written into the AD9914 on this pin. However,

this pin can be used as a bidirectional data line. Bit 1 of CFR1

(0x00) controls the configuration of this pin. The default is

Logic 0, which configures the SDIO pin as bidirectional.

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