X98021 datasheet(24/29 Pages) RENESAS

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X98021

FN8219 Rev 3.00

Page 24 of 29

March 8, 2006

Initialization

The X98021 initializes with default register settings for an AC-

coupled, RGB input on the VGA1 channel, with a 24 bit output.

The following registers should be written to fully enable the

chip:

• Register 0x1C should be set to 0x49 to improve DPLL

performance in video modes

• Register 0x23 should be set to 0x78 to enable the DC

Restore function

Reset

The X98021 has a Power-On Reset (POR) function that resets

the chip to its default state when power is initially applied,

including resetting all the registers to their default settings as

described in the Register Listing. The external RESET pin

duplicates the reset function of the POR without having to

cycle the power supplies. The RESET pin does not need to be

used in normal operation and can be tied high.

Rare CSYNC Considerations

Intersil has discovered one anomaly in its sync separator

function. If the CSYNC signal shown in Figure 11 is present on

the HSYNC input, and the sync source is set to CSYNC on

HSYNC, HSOUT may sporadically lock to the wrong edge of

HSYNCIN. This will cause the HSOUT to have the wrong

position relative to pixel 0, resulting in the image shifting left or

right by the width of the HSYNCIN signal for about 1 second

before it corrects itself.

This only happens with the exact waveshape shown in Figure

11. If the polarity of the sync signal is inverted from that shown

in Figure 11, the problem will not occur. If there are any

serrations during the VSYNC period, the problem will not

occur. The problem also will not occur if the sync signal is on

the SOG input.

This is a rarely used composite sync format; in most

applications it will never be encountered. However if this

CSYNC waveform must be supported, there is a simple

applications solution using an XOR gate.

HSYNC

(to A and B)

PIXELCLK (A)

(Internal)

DATA

PRI (A)

OUT (A)

DPLL Lock Edge

½ PIXELCLK = ¼ DATACLK Delay

CLKINV

IN (A) = GNDD

N-3 PN-2

N-1

Analog Video In

(to A and B)

DATA

SEC (A)

DATACLK (A)

N-3

N-1

CLKINV

IN (B) = GNDD

N-2

PIXELCLK (B)

(Internal)

DATA

PRI (B)

OUT (B)

DATA

SEC (B)

DATACLK (B)

FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)

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