X98021 datasheet(12/29 Pages) RENESAS

12 / 29 page

X98021

FN8219 Rev 3.00

Page 12 of 29

March 8, 2006

0x05

Input configuration (0x00)

Channel Select

0: VGA1

1: VGA2

Input Coupling

0: AC coupled (positive input connected to clamp DAC

during clamp time, negative input disconnected from outside

pad and always internally tied to appropriate clamp DAC)

1: DC coupled (+ and - inputs are brought to pads and never

connected to clamp DACs). Analog clamp signal is turned off

in this mode.

RGB/YUV

0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale

analog shift for R, G, and B, base ABLC™ target code = 0x00

for R, G, and B)

1: YUV inputs (Clamp DAC = 600mV for R and B, 300mV for

G, half scale analog shift for G channel only, base ABLC™

target code = 0x00 for G, = 0x80 for R and B)

Sync Type

0: Separate HSYNC/VSYNC

1: Composite (from SOG or CSYNC on HSYNC)

Composite Sync

Source

0: SOGIN

1: HSYNCIN

Note: If Sync Type = 0, the multiplexer will pass HSYNCIN

regardless of the state of this bit.

5COAST CLAMP

enable

0: DC restore clamping and ABLC™ suspended during

COAST

1: DC restore clamping and ABLC™ continue during COAST

7:6

Reserved

Set to 00.

0x06

Red Gain (0x55)

7:0

Red Gain

Channel gain, where:

gain (V/V) = 0.5 + [7:0]/170

0x00: gain = 0.5 V/V

(1.4VP-P input = full range of ADC)

0x55: gain = 1.0 V/V

(0.7VP-P input = full range of ADC)

0xFF: gain = 2.0 V/V

(0.35VP-P input = full range of ADC)

0x07

Green Gain (0x55)

7:0

Green Gain

0x08

Blue Gain (0x55)

7:0

Blue Gain

0x09

Red Offset (0x80)

7:0

Red Offset

ABLC™ enabled: digital offset control. A 1 LSB change in

this register will shift the ADC output by 1 LSB.

ABLC™ disabled: analog offset control. These bits go to the

upper 8 bits of the 10 bit offset DAC. A 1LSB change in this

DAC range = 0) or 0.5LSBs (Offset DAC range = 1).

0x00 = min DAC value or -0x80 digital offset,

0x80 = mid DAC value or 0x00 digital offset,

0xFF = max DAC value or +0x7F digital offset

0x0A

Green Offset (0x80)

7:0

Green Offset

0x0B

Blue Offset (0x80)

7:0

Blue Offset

0x0C

Offset DAC Configuration (0x00)

Offset DAC Range

0: ±1/2 ADC fullscale (1 DAC LSB ~ 1 ADC LSB)

1: ±1/4 ADC fullscale (1 DAC LSB ~ 1/2 ADC LSB)

Reserved

Set to 0.

3:2

Red Offset DAC LSBs These bits are the LSBs necessary for 10 bit manual offset

DAC control.

Combine with their respective MSBs in registers 0x09, 0x0A,

and 0x0B to achieve 10 bit offset DAC control.

5:4

Green Offset DAC

LSBs

7:6

Blue Offset DAC

LSBs

ADDRESS

BIT(s)

FUNCTION NAME

DESCRIPTION

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