X98021 datasheet(10/29 Pages) RENESAS

10 / 29 page

X98021

FN8219 Rev 3.00

Page 10 of 29

March 8, 2006

HSOUT

125

3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.

This output is always purely horizontal sync (without any composite sync signals)

VSOUT

126

3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after

the trailing edge of HSOUT. This signal is usually not needed - use VSYNCOUT as VSYNC source.

HSYNCOUT

127

3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC

period. HSOUT should be used to detect the beginning of a line. This output will pass composite sync signals

and Macrovision signals if present on HSYNCIN or SOGIN.

VSYNCOUT

128

3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the

duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a

frame and measure the VSYNC period.

6, 11, 18, 20,

29, 35

Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GNDA with 0.1µF.

GNDA

3, 5, 8, 10, 15,

17, 21, 23, 27,

30, 36

Ground return for VA and VBYPASS.

54, 67, 77, 89,

99, 111, 124

Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GNDD with 0.1µF.

GNDD

32, 43, 51, 53,

66, 76, 78, 88,

98, 108, 110,

120, 123

Ground return for VD, VCORE, VCOREADC, and VPLL.

Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GNDX with 0.1µF.

GNDX

Ground return for VX.

VBYPASS

4, 9, 16

Bypass these pins to GNDA with 0.1µF. Do not connect these pins to each other or anything else.

VREGIN

3.3V input voltage for VCORE voltage regulator. Connect to a 3.3V source, and bypass to GNDD with 0.1µF.

VREGOUT

Regulated output voltage for VPLL, VCOREADC and VCORE; typically 1.9V. Connect only to VPLL,

VCOREADC and VCORE and bypass at input pins as instructed below. Do not connect to anything else - this

output can only supply power to VPLL, VCOREADC and VCORE.

VCOREADC

Internal power for the ADC’s digital logic. Connect to VREGOUT through a 10 resistor and bypass to GNDD

with 0.1µF.

VPLL

Internal power for the PLL’s digital logic. Connect to VREGOUT through a 10 resistor and bypass to GNDD

with 0.1µF.

VCORE

52, 79, 109

Internal power for core logic. Connect to VREGOUT and bypass each pin to GNDD with 0.1µF.

1, 2, 63

Reserved. Do not connect anything to these pins.

Pin Descriptions (Continued)

SYMBOL

DESCRIPTION

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