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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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X98021 датащи(PDF) 18 Page - Renesas Technology Corp |
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X98021 датащи(HTML) 18 Page - Renesas Technology Corp |
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18 / 29 page  X98021 FN8219 Rev 3.00 Page 18 of 29 March 8, 2006 SYNC Processing The X98021 can process sync signals from 3 different sources: discrete HSYNC and VSYNC, composite sync on the HSYNC input, or composite sync from a Sync-On-Green (SOG) signal embedded on the Green video input. The X98021 has SYNC activity detect functions to help the firmware determine which sync source is available. PGA The X98021’s Programmable Gain Amplifier (PGA) has a nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). The transfer function is: where GainCode is the value in the Gain register for that particular color. Note that for a gain of 1 V/V for GainCode should be 85 (0x55). This is a different center value than the 128 (0x80) value used by some other AFEs, so the firmware should take this into account when adjusting gains. The PGAs are updated by the internal clamp signal once per line. In normal operation this means that there is a maximum delay of one HSYNC period between a write to a Gain register for a particular color and the corresponding change in that channel’s actual PGA gain. If there is no regular HSYNC/SOG source, or if the external clamp option is enabled (register 0x13[5:4]) but there is no external clamp signal being generated, it may take up to 100ms for a write to the Gain register to update the PGA. This is not an issue in normal operation with RGB and YUV signals. Bandwidth and Peaking Control Register 0x0D[3:1] controls a low pass filter allowing the input bandwidth to be adjusted with three bit resolution between its default value (0x0E = 780MHz) and its minimum bandwidth (0x00, for 100MHz). Typically the higher the resolution, the higher the desired input bandwidth. To minimize noise, video signals should be digitized with the minimum bandwidth setting that passes sharp edges. 0: VGA1 0x05[0] 1: VGA2 HSYNC IN1 HSYNC1 SLICER 0x03[2:0] VSYNC IN1 SOG IN1 HSYNC2 SLICER 0x03[6:4] HSYNC IN VSYNC IN ACTIVITY 0x01[6:0] & POLARITY 0x02[5:0] DETECT HSYNC IN2 VSYNC IN2 SOG IN2 SYNC SPLITTER PLL 0x0E through 0x13 HSYNC OUT VSYNC OUT COAST GENERATION 0x11, 0x12, 0x13[2] XTAL IN XTAL OUT 0: ÷1 0x13 [6] 1: ÷2 ÷2 XTALCLOCK OUT Output Formatter 0x18, 0x19, 0x1A Pixel Data from AFE 24 R P[7:0] R S[7:0] G P[7:0] G S[7:0] B P[7:0] B S[7:0] DATACLK HS OUT VS OUT SOG IN SOG SLICER 0x1C SOG SLICER 0x1C 00, 10, 11: HSYNC IN 0x05[4:3] 01: SOG IN 1: SYNC SPLTR 0x05[3] 0: VSYNC IN CLOCKINV IN HS PIXCLK CSYNC SOURCE SYNC TYPE VSYNC DATACLK FIGURE 8. SYNC FLOW Gain V V ---- 0.5 GainCode 170 ----------------------------- + = |
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