X98021 datasheet(9/29 Pages) RENESAS

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X98021

FN8219 Rev 3.00

Page 9 of 29

March 8, 2006

Pin Descriptions

SYMBOL

DESCRIPTION

RIN1

Analog input. Red channel 1. DC couple or AC couple through 0.1µF.

GIN1

Analog input. Green channel 1. DC couple or AC couple through 0.1µF.

BIN1

Analog input. Blue channel 1. DC couple or AC couple through 0.1µF.

RGBGND1

Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.

Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the

AC-coupled configuration, but the pin should still be tied to GNDA.

SOGIN1

Analog input. Sync on Green. Connect to GIN1 through a 0.01µF capacitor in series with a 500 resistor.

HSYNCIN1

Digital input, 5V tolerant, 240mV hysteresis, 1.2k

 impedance to GNDA. Connect to channel 1's HSYNC

signal through a 680

 series resistor.

VSYNCIN1

Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.

RIN2

Analog input. Red channel 2. DC couple or AC couple through 0.1µF.

GIN2

Analog input. Green channel 2. DC couple or AC couple through 0.1µF.

BIN2

Analog input. Blue channel 2. DC couple or AC couple through 0.1µF.

RGBGND2

Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.

Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the

AC-coupled configuration, but the pin should still be tied to GNDA.

SOGIN2

Analog input. Sync on Green. Connect to GIN1 through a 0.01µF capacitor in series with a 500 resistor.

HSYNCIN2

Digital input, 5V tolerant, 240mV hysteresis, 1.2k

 impedance to GNDA. Connect to channel 2's HSYNC

signal through a 680

 series resistor.

VSYNCIN2

Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.

CLOCKINVIN

Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame

rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to

DGND if unused.

RESET

Digital input, 5V tolerant, active low, 70k

 pull-up to VD. Take low for at least 1µs and then high again to

reset the X98021. This pin is not necessary for normal use and may be tied directly to the VD supply.

XTALIN

Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for

recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V.

XTALOUT

Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for

recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V.

XTALCLKOUT

3.3V digital output. Buffered crystal clock output at fXTAL or fXTAL/2. May be used as system clock for other

system components.

SADDR

Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A

including R/W bit) when tied high.

SCL

Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.

SDA

Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.

RP[7:0]

112-119

3.3V digital output. Red channel, primary pixel data. 58K pulldown when three-stated.

RS[7:0]

100-107

3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated.

GP[7:0]

90-97

3.3V digital output. Green channel, primary pixel data. 58K pulldown when three-stated.

GS[7:0]

80-87

3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated.

BP[7:0]

68-75

3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated.

BS[7:0]

55-62

3.3V digital output. Blue channel, secondary pixel data. 58K pulldown when three-stated.

DATACLK

121

3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 48

bit mode.

DATACLK

122

3.3V digital output. Inverse of DATACLK.

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