HIP6501ACBZ datasheet(8/14 Pages) RENESAS

8 / 14 page

HIP6501A

FN4749 Rev 6.00

Page 8 of 14

December 30, 2004

Soft-Start Circuit

Soft-Start into Sleep States (S3, S4/S5)

The 5VSB POR function initiates the soft-start sequence. An

internal 10

A current source charges an external capacitor

to 5V. The error amplifiers reference inputs are clamped to a

level proportional to the SS (Soft-Start) pin voltage. As the

SS pin voltage slews from about 1.25V to 2.5V, the input

clamp allows a rapid and controlled output voltage rise.

Figure 9 shows the soft-start sequence for the typical

application start-up in a sleep state with all output voltages

enabled. At time T0 5VSB (bias) is applied to the circuit. At

time T1, 5VSB surpasses POR level, and an internal fast

charge circuit quickly raises the SS capacitor voltage to

approximately 1V. At this point, the 10

A current source

continues the charging up to T2, where a voltage of 1.25V

(typically) is reached and an internal clamp limits further

charging. Clamping of the soft-start voltage (T2 to T3

interval) should only be noticed with capacitors smaller than

0.1

F; soft-start capacitors of 0.1F and above should

present a soft-start ramp void of this plateau. At time T3,

3ms (typically) past the 5VSB POR (T1), the memory output

voltage selection is latched in and the charging of the soft-

start capacitor resumes, using the 10

A current source. At

this point, the error amplifiers’ reference inputs are starting

their transitions, causing the output voltages to ramp up

proportionally. The ramping continues until time T4 when all

the voltages reach the set value. At time T5, when the soft-

start capacitor value reaches approximately 2.8V, the under-

voltage monitoring circuits are activated and the soft-start

capacitor is quickly discharged down to the value attained at

time T2 (approximately 1.25V).

FIGURE 6. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR

EN3VDL = 0, EN5VDL = 1

FIGURE 7. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR

EN3VDL = 0, EN5VDL = 0

FIGURE 8. 2.5/3.3VMEM TIMING DIAGRAM

5VSB

12V

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

5VSB

12V

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

5VSB

12V

DRV2

VSEN2

INTERNAL

DEVICE

FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE (ALL

OUTPUTS ENABLED)

TIME

SOFT-START

(1V/DIV)

OUTPUT

(1V/DIV)

VOLTAGES

VOUT1 (3.3VDUAL)

VOUT2 (2.5VMEM)

VOUT3 (5VDUAL)

T1 T2 T3

5VSB

(1V/DIV)

UV DETECT ENABLE

(LOGIC LEVEL)

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