HIP6501A

FN4749 Rev 6.00

Page 7 of 14

December 30, 2004

Very similarly, Table 2 details the fact that EN5VDL status

(Suspend-To-RAM), but not in S4/S5 state. The dual-voltage

support accommodates both SDRAM as well as RDRAM

type memories.

Additionally, the internal circuitry does not allow the

transition from an S3 (suspend to RAM) state to an S4/S5

(suspend to disk/soft off) state or vice versa. The only ‘legal’

transitions are from an active state (S0, S1) to a sleep state

(S3, S4/S5) and vice versa.

Functional Timing Diagrams

Figures 4-8 are timing diagrams, detailing the power

up/down sequences of all three outputs in response to the

status of the enable (EN3VDL, EN5VDL) and sleep-state

pins (S3, S5), as well as the status of the ATX supply.

The status of the EN3VDL and EN5VDL pins can only be

changed while in active (S0, S1) states, when the bias

supply (5VSB pin) is below POR level, or during chip

shutdown (SS pin shorted to GND); a status change of these

two pins while in a sleep state is ignored.

Not shown in these diagrams is the de-glitching feature used

to protect against false sleep state tripping. Once the status

of the S3 pin changes, an internal timer is activated. If at the

end of the timeout period (typically 200

s) the input pins

present a valid state change request, then the controller

transitions to the new configuration. Otherwise, the

previously attained valid state is maintained until valid

control signals are received from the system. This particular

feature is useful in noisy computer environments if the

control signals have to travel over significant distances.

EN5VDL

S5

S3

5VDL

COMMENTS

0

1

1

5V

S0, S1 STATES (Active)

01

0

0V

S3

0

0

1

Note 5 Maintains Previous State

00

0

0V

S4/S5

1

1

1

5V

S0, S1 STATES (Active)

11

0

5V

S3

1

0

1

Note 5 Maintains Previous State

10

0

5V

S4/S5

NOTE:

5. Combination not allowed.

S5

S3

COMMENTS

1k



1

1

2.5V

S0, S1 STATES (Active)

1k



1

0

2.5V

S3

1k



0

1

Note 6

Maintains Previous State

1k



00

0V

S4/S5

10k



1

1

3.3V

S0, S1 STATES (Active)

10k



1

0

3.3V

S3

10k



0

1

Note 6

Maintains Previous State

10k



00

0V

S4/S5

NOTE:

6. Combination not allowed.

EN3VDL = 1, EN5VDL = 1

EN3VDL = 1, EN5VDL = 0

5VSB

12V

S3

S5

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

5VSB

12V

S3

S5

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL