HIP6501A

FN4749 Rev 6.00

Page 6 of 14

December 30, 2004

provide a controlled voltage slew rate during active-to-sleep

12V (Pin 14)

Connect this pin to the ATX (or equivalent) 12V output. This

pin is used to monitor the status of the power supply as well

as provide bias for the NMOS-compatible output drivers.

12V presence at the chip in the absence of bias voltage, or

severe 12V brownout during active states (S0, S1) operation

can lead to chip misbehavior.

VSEN2 (Pin 16)

through an internal pass transistor capable of delivering

active-state voltage at this pin is regulated through an

external NPN transistor connected at the DRV2 pin. For the

3.3V setting, the ATX 3.3V is passed to this pin through a

fully on N-MOS transistor. During all operating states, the

voltage at this pin is monitored for under-voltage events.

DRV2 (Pin 15)

For the 2.5V RDRAM systems, connect this pin to the base

of a suitable NPN transistor. This pass transistor regulates

the 2.5V output from the ATX 3.3V during active states

operation. For 3.3V SDRAM systems connect this pin to the

gate of a suitable N-MOS transistor; this transistor is used to

switch in the ATX 3.3V output.

3V3DL (Pin 4)

states, the voltage at this pin is regulated to 3.3V; in active

states, ATX 3.3V output is delivered to this node through a

fully on N-MOS transistor. During all operating states, this

pin is monitored for under-voltage events.

3V3DLSB (Pin 3)

Connect this pin to the base of a suitable NPN transistor. In

sleep states, this transistor is used to regulate the voltage at

the 3V3DL pin to 3.3V.

DLA (Pin 10)

Connect this pin to the gates of suitable N-MOSFETs, which

in active states, are used to switch in the ATX 3.3V and 5V

respectively.

5VDL (Pin 12)

operating state, the voltage at this pin is provided through a

fully on MOS transistor. This pin is also monitored for under-

voltage events.

5VDLSB (Pin 11)

Connect this pin to the gate of a suitable P-MOSFET or

bipolar PNP. In sleep states, this transistor is switched on,

output.

Description

Operation

The HIP6501A controls 3 output voltages (Refer to Figures

1, 2, and 3). It is designed for microprocessor computer

applications with 3.3V, 5V, 5VSB, and 12V outputs from an

ATX power supply. The IC is composed of two linear

addition, all the control and monitoring functions necessary

for complete ACPI implementation are integrated into the

HIP6501A.

Initialization

The HIP6501A automatically initializes upon receipt of input

power. The Power-On Reset (POR) function continually

monitors the 5VSB input supply voltage, initiating soft-start

operation after it exceeds its POR threshold (in either S3 or

S4/S5 states). To ensure stabilization of the 5VSB supply

before operation is allowed, POR is released 3.3ms

(typically) after 5VSB exceeds the POR threshold. The

5VSB POR trip event is also used to lock in the memory

Operational Truth Tables

The EN3VDL and EN5VDL pins offer a host of choices in

terms of the overall system architecture and supported

features. Tables 1-3 describe the truth combinations

pertaining to each of the three outputs.

As seen in Table 1, EN3VDL simply controls whether the

3.3VDUAL plane remains powered up during S4/S5 sleep

state.

EN3VDL

S5

S3

3V3DL

COMMENTS

0

1

1

3.3V

S0, S1 STATES (Active)

01

0

3.3V

S3

0

0

1

Note 4 Maintains Previous State

00

0

3.3V

S4/S5

1

1

1

3.3V

S0, S1 STATES (Active)

11

0

3.3V

S3

1

0

1

Note 4 Maintains Previous State

10

0

0V

S4/S5

NOTE:

4. Combination not allowed.