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LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

For the SiR158DP MOSFET, this exercise yields the plot

in Figure 6.

1ms

10ms

100ms

10s

BVDSS LIMITED

ID LIMITED

IDM LIMITED

LIMITED BY RDS(ON)*

MOSFET POWER

DISSIPATION CURVE

RESULTING FROM

FOLDBACK ACTIVE

CURRENT LIMIT

TA = 25°C, SINGLE PULSE

VDS – DRAIN-TO-SOURCE VOLTAGE (V)

4236 F06

* VGS > MINIMUM VGS AT WHICH RDS(ON) IS SPECIFIED

0.01

100

0.1

100

0.1

0.01

Figure 6. SiR158DP SOA with Design Example

MOSFET Power Dissipation Superimposed

Ascanbeseen,theLTC4236’sfoldbackcurrentlimitprofile

roughly coincides with the 100ms SOA contour. Since

this SOA plot is for an ambient temperature of 25°C only,

a maximum fault timer period of much less than 100ms

should be considered, such as 10ms or less. Selecting a

0.1µF ±10% value for CFT yields a maximum fault timer

period of 1.75ms which should be small enough to protect

the MOSFET during any overcurrent fault scenario.

Next, select the values for the resistive divider at the ON

pin that defines the undervoltage threshold of 9.7V for the

12V supply at SENSE+. Since the leakage current for the

ON pin can be as high as ±1µA, the total resistance in the

divider should be low enough to minimize the resulting

offset error. Calculate the bottom resistor R1 based on

the following equation to obtain less than ±0.2% error

due to leakage current.

R1=

VON(TH)

IIN(LEAK)

⎛

⎝

⎜

⎞

⎠

⎟ • 0.2% =

1.235V

1µA

⎛

⎝⎜

⎞

⎠⎟

• 0.2% = 2.4k

Choose R1 to be 2k to achieve less than ±0.2% error and

calculating R2 yields:

R2 =

VIN(UV)

VON(TH)

– 1

⎛

⎝

⎜

⎞

⎠

⎟ • R1

R2 =

9.7V

1.235V

– 1

⎛

⎝⎜

⎞

⎠⎟

• 2k = 13.7k

It remains to select the values for the FB pin resistive

divider in order to set a power good threshold of 10.5V.

Keeping in mind the FB pin’s ±1µA leakage current, choose

a value of 2k for the bottom resistor R3. Calculating the

top resistor R4 value yields:

R4 =

VOUT(PG)

VFB(TH)

– 1

⎛

⎝

⎜

⎞

⎠

⎟ • R3

R4 =

10.5V

1.235V

– 1

⎛

⎝⎜

⎞

⎠⎟

• 2k = 15k

The subsequent offset error due to the FB pin leakage

current will be less than ±0.2%.

The final components to consider are a 0.1µF bypass (C1)

at the INTVCC pin and a 0.1µF capacitor (C4) connected

between the REG and SENSE+ pins.

PCB Layout Considerations

To achieve accurate current sensing, a Kelvin connection

for the sense resistor is recommended. The PCB layout

should be balanced and symmetrical to minimize wiring

errors. In addition, the PCB layout for the sense resistor

and the power MOSFET should include good thermal

managementtechniquesforoptimaldevicepowerdissipa-

tion. A recommended PCB layout is illustrated in Figure 7.

Connect the IN and OUT pin traces as close as possible to

the MOSFETs’ terminals. Keep the traces to the MOSFETs

wideandshorttominimizeresistivelosses.ThePCBtraces

associated with the power path through the MOSFETs

should have low resistance. The suggested trace width for

1oz copper foil is 0.03" for each ampere of DC current to

keep PCB trace resistance, voltage drop and temperature

rise to a minimum. Note that the sheet resistance of 1oz

copper foil is approximately 0.5mΩ/square, and voltage

drops due to trace resistance add up quickly in high cur-

rent applications.

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