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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LTC6945 датащи(PDF) 5 Page - Linear Technology |
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LTC6945 датащи(HTML) 5 Page - Linear Technology |
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5 / 24 page  5 2271f LTC2271 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Single-Ended Encode Mode (ENC– Tied to GND) VIH High Level Input Voltage VDD =1.8V l 1.2 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V VIN Input Voltage Range ENC+ to GND l 0 3.6 V RIN Input Resistance See Figure 11 30 kΩ CIN Input Capacitance (Note 8) 3.5 pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD =1.8V l 1.3 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 μA CIN Input Capacitance (Note 8) 3 pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used) ROL Logic Low Output Resistance to GND VDD =1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 μA COUT Output Capacitance (Note 8) 3 pF DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 mV mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 V V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 93.3 103 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode l l l l l l 9.4 17.5 13.4 25.5 21.9 42 10.7 19.6 15.5 29 25 47 mA mA mA mA mA mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode l l l l l l 185 199 192 214 207 244 205 221 214 238 231 270 mW mW mW mW mW mW PSLEEP Sleep Mode Power 1mW PNAP Nap Mode Power 50 mW PDIFFCLK Power Increase with Diffential Encode Mode Enabled (No Increase for Sleep Mode) 20 mW |
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