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LTC6945 датащи(PDF) 6 Page - Linear Technology

номер детали LTC6945
подробное описание детали  16-Bit, 20Msps Serial Low Noise Dual ADC
PDF  24 Pages
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
Logo LINER - Linear Technology

LTC6945 датащи(HTML) 6 Page - Linear Technology

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LTC2271
6
2271f
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
(Note 10)
l
5
20
MHz
tENCL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
23.5
2
25
25
100
100
ns
ns
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
23.5
2
25
25
100
100
ns
ns
tAP
Sample-and-Hold
Acquistion Delay Time
0ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 20MHz, 2-lane output mode,
differential ENC+/ENC= 2VP-P sine wave, input range = 2.1VP-P with
differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD=1.8V, fSAMPLE = 20MHz, 2-lane output mode, ENC+
= single-ended 1.8V square wave, ENC= 0V, input range = 2.1VP-P with
differential drive, unless otherwise noted. The supply current and power
dissipation specifications are totals for the entire IC, not per channel.
Note 10: Recommended operating conditions.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output)
tSER
Serial Data Bit Period
4-Lane Output Mode
2-Lane Output Mode
1-Lane Output Mode
1/(4 • fS)
1/(8 • fS)
1/(16 • fS)
Sec
tFRAME
FR to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
Sec
tDATA
Data to DCO Delay
(Note 8)
l
0.35 • tSER
0.5 • tSER
0.65 • tSER
Sec
tPD
Propagation Delay
(Note 8)
l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER
Sec
tr
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tf
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 3.1ns
60
psP-P
Pipeline Latency
7
7
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
Write Mode
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
tS
CS-to-SCK Setup Time
l
5ns
tH
SCK-to-CS Setup Time
l
5ns
tDS
SDI Setup Time
l
5ns
tDH
SDI Hold Time
l
5ns
tDO
SCK Falling to SDO
Valid
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
l
125
ns



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