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2271f

LTC2271

APPLICATIONS INFORMATION

DIGITAL OUTPUTS

The digital outputs of the LTC2271 are serialized LVDS

signals. Each channel outputs one bit at a time (1-lane

mode), two bits at a time (2-lane mode) or four bits at a

time (4-lane mode). Please refer to the Timing Diagrams

for details. In 4-lane mode the clock duty cycle stabilizer

must be enabled.

The output data should be latched on the rising and falling

edges of the data clock out (DCO). A data frame output

(FR) can be used to determine when the data from a new

conversion result begins.

The minimum sample rate for all serialization modes is

5Msps.

By default the outputs are standard LVDS levels: 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100Ω differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

The outputs are powered by OVDD which is isolated from

the A/D core power.

Table 1. Maximum Sampling Frequency for All Serialization

Modes

SERIALIZATION

MODE

MAXIMUM

SAMPLING

FREQUENCY,

fS (MHz)

DCO

FREQUENCY

SERIAL

DATA RATE

4-Lane

2 • fS

4 • fS

2-Lane

4 • fS

8 • fS

1-Lane

8 • fS

16 • fS

Programmable LVDS Output Current

In LVDS mode, the default output driver current is 3.5mA.

This current can be adjusted by control register A2 in the

serial programming mode. Available current levels are

1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

In the parallel programming mode the SDO pin can select

either 3.5mA or 1.75mA.

Optional LVDS Driver Internal Termination

In most cases using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100Ω termination resistor can

be enabled by serially programming mode control register

A2. The internal termination helps absorb any reﬂections

caused by imperfect termination at the receiver. When

the internal termination is enabled, the output driver

current is doubled to maintain the same output voltage

swing. Internal termination can only be selected in serial

programming mode.

DATA FORMAT

Table 2 shows the relationship between the analog input

voltage and the digital data output bits. By default the

output data format is offset binary. The 2’s complement

format can be selected by serially programming mode

control register A1.

Table 2. Output Codes vs Input Voltage

AIN+-AIN–

(2V RANGE)

D15-D0

(OFFSET BINARY)

D15-D0

(2’s COMPLEMENT)

>1.000000V

+0.999970V

+0.999939V

1111 1111 1111 1111

1111 1111 1111 1110

0111 1111 1111 1111

0111 1111 1111 1110

+0.000030V

+0.000000V

–0.000030V

–0.000061V

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

0111 1111 1111 1110

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

–0.999939V

–1.000000V

<–1.000000V

0000 0000 0000 0001

0000 0000 0000 0000

1000 0000 0000 0001

1000 0000 0000 0000

Digital Output Randomizer

Interference from the A/D digital outputs is sometimes

unavoidable. Digital interference may be from capacitive or

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off-chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

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