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LTC2271

2271f

Encode Input

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12, 13). The

encode inputs are internally biased to 1.2V through 10k

equivalent resistance. The encode inputs can be taken above

VDD(upto3.6V),andthecommonmoderangeisfrom1.1V

to 1.6V. In the differential encode mode, ENC– should stay

at least 200mV above ground to avoid falsely triggering the

single-ended encode mode. For good jitter performance

ENC+ should have fast rise and fall times.

The single-ended encode mode should be used with

CMOS encode inputs. To select this mode, ENC– is con-

nected to ground and ENC+ is driven with a square wave

APPLICATIONS INFORMATION

encode input. ENC+ can be taken above VDD (up to 3.6V)

so 1.8V to 3.3V CMOS logic levels can be used. The ENC+

threshold is 0.9V. For good jitter performance ENC+ should

have fast rise and fall times. If the encode signal is turned

off or drops below approximately 500kHz, the A/D enters

nap mode.

Figure 12. Sinusoidal Encode Drive

ENC+

ENC–

PECL OR

LVDS

CLOCK

0.1μF

2271 F13

LTC2271

Figure 13. PECL or LVDS Encode Drive

50Ω

100Ω

0.1μF

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

LTC2271

2271 F12

ENC–

ENC+

0.1μF

VDD

LTC2271

2271 F10

ENC–

ENC+

15k

VDD

DIFFERENTIAL

COMPARATOR

30k

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

30k

ENC+

ENC–

2271 F11

1.8V TO 3.3V

LTC2271

CMOS LOGIC

BUFFER

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

Clock PLL and Duty Cycle Stabilizer

The encode clock is multiplied by an internal phase-locked

loop (PLL) to generate the serial digital output data. If the

encode signal changes frequency or is turned off, the PLL

requires 25μs to lock onto the input clock.

A clock duty cycle stabilizer circuit allows the duty cycle

of the applied encode signal to vary from 30% to 70%.

In the serial programming mode it is possible to disable

the duty cycle stabilizer, but this is not recommended. In

the parallel programming mode the duty cycle stabilizer

is always enabled.

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