LTC6945 datasheet(12/24 Pages) LINER

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LTC2271

2271f

SENSE (Pin 50): Reference Programming Pin. Connecting

SENSE to VDD selects the internal reference and a ±1.05V

input range. Connecting SENSE to ground selects the

internal reference and a ±0.525V input range. An external

reference between 0.625V and 1.3V applied to SENSE

selects an input range of ±0.84 • VSENSE.

LVDS Outputs

The following pins are differential LVDS outputs. The

output current level is programmable. There is an optional

internal 100Ω termination resistor between the pins of

each LVDS output pair.

PIN FUNCTIONS

OUT2D–/OUT2D+, OUT2C–/OUT2C+, OUT2B–/OUT2B+,

OUT2A–/OUT2A+ (Pins 23/24, 25/26, 27/28, 29/30):

Serial

Data Outputs for Channel 2. In 1-lane output mode only

OUT2A–/OUT2A+ are used. In 2-Lane output mode only

OUT2A–/OUT2A+ and OUT2B–/OUT2B+ are used.

FR–/FR+ (Pins 31/32):

Frame Start Outputs.

DCO–/DCO+ (Pins 35/36):

Data Clock Outputs.

OUT1D–/OUT1D+, OUT1C–/OUT1C+, OUT1B–/OUT1B+,

OUT1A–/OUT1A+ (Pins 37/38, 39/40, 41/42, 43/44):

Serial

Data Outputs for Channel 1. In 1-lane output mode only

OUT1A–/OUT1A+ are used. In 2-lane output mode only

OUT1A–/OUT1A+ and OUT1B–/OUT1B+ are used.

FUNCTIONAL BLOCK DIAGRAM

DIFF REF

AMP

REF BUF

2.2μF

1μF

REFH

REFL

RANGE

SELECT

1.25V

REFERENCE

REFH

REFL

VCM1

VCM2

VDD/2

SDO

2271 F01

S/H

SENSE

VREF

2.2μF

MODE

CONTROL

REGISTERS

SCK

PAR/SER

SDI

16-BIT

ADC CORE

CH2

ANALOG

INPUT

CH1

ANALOG

INPUT

S/H

16-BIT

ADC CORE

OUT1A

OUT1B

OUT1C

OUT1D

OUT2A

OUT2B

OUT2C

OUT2D

DATA CLOCK OUT

FRAME

DATA

SERIALIZER

OGND

OVDD

ENC–

VDD

ENC+

1.8V

PLL

Figure 1. Functional Block Diagram

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