ADP3166 datasheet(19/20 Pages) AD

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ADP3166

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Power Circuitry

• The switching power path should be routed on the PCB to

encompass the shortest possible length to minimize radiated

switching noise energy (i.e., EMI) and conduction losses in

the board. Failure to take proper precautions often results in

EMI problems for the entire PC system as well as noise-

related operational problems in the power converter control

circuitry. The switching power path is the loop formed by

the current path through the input capacitors and the power

MOSFETs including all interconnecting PCB traces and

planes. The use of short and wide interconnection traces is

especially critical in this path for two reasons: it minimizes

the inductance in the switching loop, which can cause high

energy ringing, and it accommodates the high current

demand with minimal voltage loss.

• Whenever a power dissipating component (e.g., a power

MOSFET) is soldered to a PCB, the liberal use of vias, both

directly on the mounting pad and immediately surrounding

it, is recommended. Two important reasons for this are

improved current rating through the vias, and improved

thermal performance from vias extended to the opposite side

of the PCB where a plane can more readily transfer the heat

to the air. Make a mirror image of any pad being used to

heatsink the MOSFETs on the opposite side of the PCB to

achieve the best thermal dissipation to the air around the

board. To further improve thermal performance, the largest

possible pad area should be used.

• The output power path should also be routed to encompass

a short distance. The output power path is formed by the

current path through the inductor, the output capacitors,

and the load.

• For best EMI containment, a solid power ground plane

should be used as one of the inner layers extending fully

under all the power components.

Signal Circuitry

• The output voltage is sensed and regulated between the

FB pin and the FBRTN pin, which connects to the signal

ground at the load. To avoid differential mode noise pickup

in the sensed signal, the loop area should be small. Therefore

the FB and FBRTN traces should be routed adjacent to each

other on top of the power ground plane back to the controller.

• The feedback traces from the switch nodes should be con-

nected as close as possible to the inductor. The CSREF

signal should be connected to the output voltage at the

inductor nearest to the controller.

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