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ADP3166 датащи(PDF) 13 Page - Analog Devices |
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ADP3166 датащи(HTML) 13 Page - Analog Devices |
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13 / 20 page ![]() REV. 0 ADP3166 –13– 4. Compute the relative values for RCS1, RCS2, and RTH using R= A– B r r – A – Br + B – A r A– B r – B – A r – A – B R= 1– A –R – A r– R R= –R – R CS CS CCS TH CS CS 2 12 2 1 12 1 21 2 21 11 11 1 1 1 1 1 1 ()×× × ()××()× × ()××()× () () S (8) 5. Calculate RTH = rTH RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k= R R TH ACTUAL TH CALCULATED () () (9) 6. Finally, calculate values for RCS1 and RCS2 using the following: R= R k R R= R - k + k R CS CS CS CS CS CS 11 22 1 ×× × () × () () (10) For this example, RCS has been chosen to be 100 k Ω, so we start with a thermistor value of 100 k Ω. Looking through available 0603 size thermistors, we find a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these we compute RCS1 = 0.3796, RCS2 = 0.7195 and RTH = 1.0751. Solving for RTH yields 107.51 k Ω, so we choose 100 kΩ, mak- ing k = 0.9302. Finally, we find RCS1 and RCS2 to be 35.3 k Ω and 73.9 k Ω. Choosing the closest 1% resistor values yields a choice of 35.7 k Ω and 73.2 kΩ. Output Offset AMD’s specification requires that at no load, the nominal output voltage of the regulator be offset to a higher value than the nominal voltage corresponding to the VID code. The offset is set by a con- stant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 11: R= V– V I R= .V – . V A =. k B ONL VID FB B 153 1 5 15 200 µ Ω (11) The closest standard 1% resistor value is 2.00 k Ω. COUT Selection The required output decoupling for the regulator is typically recommended by AMD for various processors and platforms. One can also use some simple design guidelines to determine what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. The first thing is to select the total amount of ceramic capaci- tance, which is based on the number and type of capacitor to be used. The best location for ceramics is inside the socket. Others can be placed along the outer edge of the socket as well. Combined ceramic values of 30 µF to 100 µF are recommended, usually made up of multiple ceramic capacitors. Select the num- ber of ceramics and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when one considers the VID on-the-fly voltage stepping of the output (voltage step VV in time tV with error of VERR) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step ∆I O: C LI nR V C X MIN O OD VID Z () – ≥ × ×× ∆ (12) C L nK R V V +t V V nK R L –1 – C XMAX 2 O V VID V VID V O Z () ≤ ×× × ×× ×× 2 2 1 (13) where K –In V V ERR V To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than or equal to the dynamic droop resistance, ROD. If the CX(MIN) is larger than CX(MAX), the system will not meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may have to increase the switch- ing frequency to keep the output ripple the same). For our example, a combination of MLCC capacitors (CZ = 50 µF) was used. The VID on-the-fly step change is from 1.5 V to 0.8 V (making VV = 700 mV) in 100 µs with a setting error of 3%. Solving for the bulk capacitance yields C nH A mV FmF X MIN () .. –. ≥ × ×× µ = 600 24 31 9 1 5 50 1 63 Ω C nH mV .. V + ms . V . . m mV nH –– mF =. mF XMAX 2 () ≤ × ×× × ×× × × × 600 700 33 5 1 5 1 100 1 5 3 3 5 1 1 700 600 150 20 4 2 Ω where K = 3.5. Using eight 820 µF OSCONs with a typical ESR of 12 mΩ each yields CX = 6.56 mF with an RX = 1.5 m Ω. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the initial high fre- quency transient spike. This is tested using LC R LmF . mW =pH XZ OD X ≥× × ≥× × 2 250 1 9 361 2 2 (14) |
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