ADP3166 datasheet(17/20 Pages) AD

17 / 20 page

REV. 0

ADP3166

–17–

to further derate the capacitor, or to choose a capacitor rated at

a higher temperature than required. Several capacitors may be

placed in parallel to meet size or height requirements in the

design. In this example, the input capacitor bank is formed by

three 2200

µF, 16 V Nichicon capacitors with a ripple current

rating of 3.5 A each.

To reduce the input-current di/dt to below the recommended

maximum of 0.1 A/

µs, an additional small inductor (L > 1 µH

@ 15 A) should be inserted between the converter and the sup-

ply bus. That inductor also acts as a filter between the converter

and the primary power source.

R= R

V–V

CS2 NEW

CS2 OLD

FLCOLD

FLHOT

()

(

) ×

()

(35)

TUNING PROCEDURE FOR ADP3166

Build a circuit based on compensation values computed

from the design spreadsheet.

Hook up the dc load to the circuit, turn it on, and verify its

operation. Also check for jitter at no load and full load.

DC Loadline Setting

Measure the output voltage at no load (VNL). Verify that

it is within tolerance.

Measure the output voltage at full load cold (VFLCOLD). Let

the board set for a ~10 minutes at full load and measure

output (VFLHOT). If there is a change of more than a few

millivolts, adjust RCS1 and RCS2 using Equations 35 and 37.

Repeat Step 4 until the cold and hot voltage measurements

remain the same.

Measure the output voltage from no load to full load using 5

A steps. Compute the loadline slope for each change and

then average them to get the overall loadline slope (ROMEAS).

If ROMEAS is off by more than 0.05 m

Ω from RO, use Equa-

tion 36 to adjust the RPH values:

R= R

PH NEW

PH OLD

OMEAS

()

(

)

(36)

Repeat Steps 6 and 7 to check the loadline and repeat the

adjustments if necessary.

Once finished with dc loadline adjustment, do not change

RPH, RCS1, RCS2, or RTH for the rest of the procedure.

10.

Measure the output ripple at no load and at full load with

a scope and make sure that it is within spec.

AC Loadline Setting

11.

Remove the dc load from the circuit and hook up the

dynamic load.

12.

Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100

µs/div.

13.

Set the dynamic load for a transient step of about 24 A at 1

kHz with 50% duty cycle.

14.

Measure the output waveform (it might be necessary to

use a dc offset on scope to see the waveform). Try to use a

vertical scale of 100 mV/div or finer.

15.

The waveform should look something like Figure 3. Use

the horizontal cursors to measure VACDRP and VDCDRP

as shown. DO NOT MEASURE THE UNDERSHOOT

OR OVERSHOOT THAT HAPPENS IMMEDI-

ATELY AFTER THE STEP.

VACDRP

VDCDRP

Figure 3. AC Loadline Waveform

16.

If the VACDRP and VDCDRP are different by more than a few

millivolts, use the following to adjust CCS. It might be

necessary to parallel different values to get the right one

since there are limited standard capacitor values available.

(It is a good idea to have locations for two capacitors in

the layout for this.)

17.

Repeat Steps 11 to 13 and repeat adjustments if neces-

sary. Once complete, do not change CCS for the rest of

the procedure.

18.

Set the dynamic load step to maximum step size (do not

use a step size larger than needed), and verify that the

output waveform is square (meaning VACDRP and VDCDRP

are equal).

R+ R

+ R

– R

–

NEW

CS OLD

OLD

CS2 NEW

OLD

()

(

)

()

()×





(37)

C= C

CS NEW

CS OLD

ACDRP

DCDRP

()

(

)

(38)

ADP3166 датащи(PDF) 17 Page - Analog Devices

ADP3166 датащи(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL