ADP3166 datasheet(14/20 Pages) AD

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ADP3166

In this example, LX is 375 pH for the eight OSCON capacitors,

which basically satisfies this limitation. If the LX of the chosen

bulk capacitor bank is too large, the number of capacitors must

be increased.

One should note for this multimode control technique, all-

ceramic designs can be used as long as the conditions of

Equations 12, 13, and 14 are satisfied.

Power MOSFETs

For this example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate

drive voltage (the supply voltage to the ADP3418) dictates

whether standard threshold or logic-level threshold MOSFETs

must be used. With VGATE ~10 V, logic-level threshold MOSFETs

(VGS(TH) < 2.5 V) are recommended.

The maximum output current, IO, determines the RDS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3166, currents are balanced between phases, thus the

current in each low-side MOSFET is the output current divided

by the total number of MOSFETs (nSF). With conduction losses

being dominant, the following expression shows the total power

being dissipated in each synchronous MOSFET in terms of the

ripple current per phase (IR) and average total output current (IO):

– D

DS SF

()×





























() (15)

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, one can find the required

RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an

ambient temperature of 50ºC, a safe limit for PSF is 1 W to 1.5 W

at 120ºC junction temperature. Thus, for our example (56 A

maximum), we find RDS(SF) (per MOSFET) < 10 m

Ω. This

RDS(SF) is also at a junction temperature of about 120ºC, so we

need to make sure we account for this when making this selection.

For our example, we selected two lower-side MOSFETs at 7 m

Ω

each at room temperature, which gives 8.4 m

Ω at high temperature.

Another important factor for the synchronous MOSFET is the

input capacitance and the feedback capacitance. The ratio of

the feedback to input needs to be small (less than 10% is recom-

mended) to prevent accidental turn-on of the synchronous

MOSFETs when the switch node goes high.

Also, the time to switch off the synchronous MOSFETs should

not exceed the nonoverlap dead time of the MOSFET driver

(40 ns typical for the ADP3418). The output impedance of the

driver is about 2

Ω and the typical MOSFET input gate resistances

are about 1

Ω to 2 Ω, so a total gate capacitance of less than

6000 pF should be adhered to. Since there are two MOSFETs in

parallel, we should limit the input capacitance for each synchro-

nous MOSFET to 3000 pF.

The high-side (main) MOSFET must be able to handle two

main power dissipation components: conduction and switching

losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off, and to the

current and voltage that are being switched. Basing the switch-

ing speed on the rise and fall time of the gate driver impedance

and MOSFET input capacitance, the following expression pro-

vides an approximate value for the switching loss per main

MOSFET, where nMF is the total number of main MOSFETs:

P= 2

SMF

ISS

()

××

(16)

Here, RG is the total gate resistance (2

Ω for the ADP3418 and

about 1

Ω for typical high speed switching MOSFETs, making

RG = 3

Ω) and C

ISS is the input capacitance of the main

MOSFET. It is interesting to note that adding more main

MOSFETs (nMF) does not really help the switching loss per

MOSFET since the additional gate capacitance slows down

switching. The best thing to reduce switching loss is to use

lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the fol-

lowing, where RDS(MF) is the on resistance of the MOSFET:

P= D

CMF

DS MF

()





























(17)

Typically, for main MOSFETs, one wants the highest speed

(low CISS) device, but these usually have higher on resistance.

One must select a device that meets the total power dissipation

(about 1.5 W for a single D-PAK) when combining the switch-

ing and conduction losses.

For our example, we have selected an Infineon IPD12N03L as the

main MOSFET (three total; nMF = 3), with a CISS = 1460 pF (max)

and RDS(MF) = 14 m

Ω (max at TJ = 120ºC) and an Infineon

IPD06N03L as the synchronous MOSFET (six total; nSF = 6),

with CISS = 2370 pF (max) and RDS(SF) = 8.4 m

Ω (max at TJ = 120ºC).

The synchronous MOSFET CISS is less than 3000 pF, satisfy-

ing that requirement. Solving for the power dissipation per

MOSFET at IO = 56 A and IR = 6.6 A yields 647 mW for each

synchronous MOSFET and 1.26 W for each main MOSFET.

These numbers work well considering there is usually more

PCB area available for each main MOSFET versus each syn-

chronous MOSFET.

One last thing to look at is the power dissipation in the driver

for each phase. This is best described in terms of the QG for the

MOSFETs and is given by the following, where QGMF is the

total gate charge for each main MOSFET and QGSF is the total

gate charge for each synchronous MOSFET:

+ n

+ I

DRV

GMF

GSF

××

()









(18)

Also shown is the standby dissipation factor (ICC

VCC) for the

driver. For the ADP3418, the maximum dissipation should be

less than 400 mW. For our example, with ICC = 7 mA, QGMF =

22.8 nC and QGSF = 34.3 nC, we find 265 mW in each driver,

which is below the 400 mW dissipation limit. See the ADP3418

data sheet for more details.

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