ADP3166 datasheet(18/20 Pages) AD

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REV. 0

–18–

ADP3166

Initial Transient Setting

19.

With dynamic load still set at maximum step size, expand

scope time scale to see 2

µs/div to 5 µs/div. The waveform

may have two overshoots and one minor undershoot (see

Figure 5). Here, VDROOP is the final desired static value.

VDROOP

VTRAN1

VTRAN2

Figure 4. Transient Setting Waveform

20.

If the overshoots are larger than desired, try making the

following adjustments in this order (Note: if these adjust-

ments do not change the response, you are limited by the

output decoupling). Check the output response each time

a change is made as well as the switching nodes (to make

sure it is still stable).

a. Make the ramp resistor larger by 25% (RRAMP).

b. For VTRAN1, increase CB or switching frequency.

c. For VTRAN2, increase RA and decrease CA by 25%.

VDROOP

VTRANREL

Figure 5. Transient Setting Waveform

21.

For load release (see Figure 5), if VTRANREL is larger

than VTRAN1 (refer to Figure 4), there is not enough

output capacitance. Either more capacitance is needed or

it is necessary to make the inductor values smaller (if

inductors are changed, it is necessary to start design over

using the spreadsheet and this tuning guide).

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal performance

of a switching regulator in a PC system. Key layout issues are

illustrated in Figure 6.

12V CONNECTOR

INPUT POWER PLANE

THERMISTOR

OUTPUT

POWER

PLANE

CPU

SOCKET

KEEP-OUT

AREA

KEEP-OUT

AREA

SWITCH NODE

PLANES

KEEP-OUT

AREA

KEEP-OUT

AREA

Figure 6. Layout Recommendations

General Recommendations

• For good results, at least a four-layer PCB is recommended.

This should allow the needed versatility for control circuitry

interconnections with optimal placement, power planes for

ground, input and output power, and wide interconnection

traces in the rest of the power delivery current paths. Keep

in mind that each square unit of 1 ounce copper trace has a

resistance of ~0.53 m

Ω at room temperature.

• Whenever high currents must be routed between PCB lay-

ers, vias should be used liberally to create several parallel

current paths so that the resistance and inductance intro-

duced by these current paths is minimized and the via current

rating is not exceeded.

• If critical signal lines (including the output voltage sense

lines of the ADP3166) must cross through power circuitry,

it is best if a signal ground plane can be interposed between

those signal lines and the traces of the power circuitry. This

serves as a shield to minimize noise injection into the signals

at the expense of making signal ground a bit noisier.

• An analog ground plane should be used around and under

the ADP3166 for referencing the components associated

with the controller. This plane should be tied to the nearest

output decoupling capacitor ground and should not be tied

to any other power circuitry to prevent power currents from

flowing in it.

• The components around the ADP3166 should be located

close to the controller with short traces. The most important

traces to keep short and away from other traces are the FB

and CSSUM pins. Refer to Figure 6 for more details on

layout for the CSSUM node.

• The output capacitors should be connected as close as

possible to the load (or connector) that receives the power

(e.g., a microprocessor core). If the load is distributed, the

capacitors should also be distributed, and generally in pro-

portion to where the load tends to be more dynamic.

• Avoid crossing any signal lines over the switching power

path loop, described below.

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