TLE5012B datasheet(28/50 Pages) INFINEON

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TLE5012B

Specification

Data Sheet

Rev. 2.0, 2014-02

4.3.7

Clock Supply (CLK Timing Definition)

The internal clock supply of the TLE5012B is subject to production-specific variations, which have to be considered

for all timing specifications.

In order to fix the IC timing and synchronize the TLE5012B with other ICs in a system, it can be switched to operate

with an external clock signal supplied to the IFC pin. The clock input signal must fulfill certain requirements:

•

The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse

width and must be spike-filtered.

•

The duty cycle factor should typically be 50%, but it can vary between 30% and 70%.

•

The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is

generated automatically and the sensor restarts with the internal clock. This is indicated by the S_RST, and

CLK_SEL bits, and additionally by the Safety Word (see Chapter 4.4.1.2).

Figure 4-6 External CLK timing definition

Table 4-11 Internal clock timing specification

Parameter

Symbol

Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Digital clock

fDIG

22.8

25.8 MHz

Internal oscillator frequency

fCLK

3.8

4.0

4.3 MHz

Table 4-12 External Clock Specification

Parameter

Symbol

Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Input frequency

fCLK

3.8

4.0

4.3 MHz

CLK duty cycle1)2)

1) Minimum duty cycle factor: tCLKh(min) / tCLK with tCLK= 1 / fCLK

2) Maximum duty cycle factor: tCLKh(max) / tCLK with tCLK= 1 / fCLK

CLKDUTY

70 %

CLK rise time

tCLKr

30 ns

From VL to VH

CLK fall time

tCLKf

30 ns

From VH to VL

tCLKh

tCLKl

tCLK

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