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TMP112BIDRLR датащи(PDF) 18 Page - Texas Instruments

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номер детали TMP112BIDRLR
подробное описание детали  High-Accuracy, Low-Power, Digital Temperature Sensors With SMBus and Two-Wire Serial Interface in SOT563
PDF  32 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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TMP112BIDRLR датащи(HTML) 18 Page - Texas Instruments

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I/O
Control
Interface
SCL
SDA
Temperature
Register
Configuration
Register
T
LOW
Register
T
HIGH
Register
Pointer
Register
18
TMP112
SBOS473F – MARCH 2009 – REVISED FEBRUARY 2018
www.ti.com
Product Folder Links: TMP112
Submit Documentation Feedback
Copyright © 2009–2018, Texas Instruments Incorporated
7.4.4.1 Comparator Mode (TM = 0)
In Comparator mode (TM = 0), the Alert pin is activated when the temperature equals or exceeds the value in the
T(HIGH) register and remains active until the temperature falls below the value in the T(LOW)register. For more
information on the comparator mode, see the High- and Low-Limit Register section.
7.4.4.2 Interrupt Mode (TM = 1)
In Interrupt mode (TM = 1), the Alert pin is activated when the temperature exceeds T(HIGH) or goes below T(LOW)
registers. The Alert pin is cleared when the host controller reads the temperature register. For more information
on the interrupt mode, see the High- and Low-Limit Register section.
7.5 Programming
7.5.1 Pointer Register
Figure 15 shows the internal register structure of the TMP112 family. The 8-bit Pointer Register of the device is
used to address a given data register. The Pointer Register uses the two LSBs (see Table 13) to identify which
of the data registers must respond to a read or write command. The power-up reset value of P1/P0 is '00'. By
default, the TMP112 family reads the temperature on power-up.
Figure 15. Internal Register Structure
Table 6 lists the pointer address of the registers available in the TMP112 family. Table 7 lists the bits of the
Pointer Register byte. During a write command, bytes P2 through P7 must always be 0.
Table 6. Pointer Addresses
P1
P0
REGISTER
0
0
Temperature Register (Read Only)
0
1
Configuration Register (Read/Write)
1
0
TLOW Register (Read/Write)
1
1
THIGH Register (Read/Write)
Table 7. Pointer Register Byte
P7
P6
P5
P4
P3
P2
P1
P0
0
0
0
0
0
0
Register Bits



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