SCL

SDA

t

(LOW)

t

RC

t

FC

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

t

(BUF)

S

S

P

P

t

RD

t

FD

14

TMP112

SBOS473F – MARCH 2009 – REVISED FEBRUARY 2018

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7.3.2.9 Timing Diagrams

operations on the TMP112 family. Parameters for Figure 10 are defined in Timing Requirements. Bus definitions

are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, when the SCL line is high, defines

a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a

STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The TMP112 family can also be used for single byte updates. To update

only the MS byte, terminate the communication by issuing a START or STOP communication on the bus.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA

line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data transfer can be signaled by the master generating a

Not-Acknowledge ('1') on the last byte that has been transmitted by the slave.

7.3.2.9.1

Two-Wire Timing Diagrams

See the Timing Requirements.

Figure 10. Two-Wire Timing Diagram