MB96310 datasheet(44/82 Pages) CYPRESS

44 / 82 page

Document Number: 002-04592 Rev. *A

Page 43 of 81

MB96310 Series

2. Opposite phase external clock

• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to

the X0 (X0A) pins.

13.4 Unused sub clock signal

If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin

must be left open.

13.5 Notes on PLL clock mode operation

If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts

to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.

13.6 Power supply pins (VCC/VSS)

It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or

VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.

VCC and VSS must be connected to the device from the power supply with lowest possible impedance.

As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1

F between VCC and VSS as close

as possible to VCC and VSS pins.

13.7 Crystal oscillator and ceramic resonator circuit

Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest

possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost

effort, that the lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area

for stabilizing the operation.

It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially

when using low-Q resonators at higher frequencies.

13.8 Turn on sequence of power supply to A/D converter and analog inputs

It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power

supply (VCC) on.

It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage

must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable).

13.9 Pin handling when not using the A/D converter

It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.

13.10 Notes on Power-on

To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than

s from 0.2 V to 2.7 V.

MB96310 датащи(PDF) 44 Page - Cypress Semiconductor