MB96310 datasheet(43/82 Pages) CYPRESS

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Document Number: 002-04592 Rev. *A

Page 42 of 81

MB96310 Series

13. Handling Devices

Special care is required for the following when handling the device:

• Latch-up prevention

• Unused pins handling

• External clock usage

• Unused sub clock signal

• Notes on PLL clock mode operation

• Power supply pins (VCC/VSS)

• Crystal oscillator circuit

• Turn on sequence of power supply to A/D converter and analog inputs

• Pin handling when not using the A/D converter

• Notes on energization

• Stabilization of power supply voltage

• Serial communication

13.1 Latch-up prevention

CMOS IC chips may suffer latch-up under the following conditions:

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.

Latch-up may increase the power supply current dramatically, causing thermal damages to the device.

13.2 Unused pins handling

Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0).

Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device.

They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 k

.

Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or

external pull-up/pull-down resistor as described above.

13.3 External clock usage

The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for

detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows:

1. Single phase external clock

• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.

MB96310 датащи(PDF) 43 Page - Cypress Semiconductor