HT67F5652 datasheet(21/224 Pages) HOLTEK

21 / 224 page

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HT67F5652

24-Bit Delta Sigma A/D + LCD Flash MCU

HT67F5652

24-Bit Delta Sigma A/D + LCD Flash MCU

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedto

theirinternalsystemarchitecture.Therangeofthedevicetakeadvantageoftheusualfeaturesfound

withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.

Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction

executionareoverlapped,henceinstructionsareeffectivelyexecutedinoneortwocyclesfor

mostofthestandardorextendedinstructionsrespectively,withtheexceptionofbranchorcall

instructionswhichneedonemorecycle.An8-bitwideALUisusedinpracticallyallinstructionset

operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,

branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulator

andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly

orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional

architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea

functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthe

devicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and Pipelining

Themainsystemclock,derivedfromeitheraHXT,LXT,HIRCorLIRCoscillatorissubdivided

intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincremented

atthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.Theremaining

T2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clock

cycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplace

inconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat

instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions

wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich

casetheinstructionwilltakeonemoreinstructioncycletoexecute.

Fet�h Inst. (PC)

Exe�ute Inst. (PC-1)

Fet�h Inst. (PC+1)

Exe�ute Inst. (PC)

Fet�h Inst. (PC+�)

Exe�ute Inst. (PC+1)

Os�illato� Clo�k

(Syste� Clo�k)

Phase Clo�k T1

Phase Clo�k T�

Phase Clo�k T3

Phase Clo�k T4

P�og�a� Counte�

Pipelining

PC+1

PC+�

System Clocking and Pipelining

Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesare

requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone

cycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe

branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming

sensitiveapplications.

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