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HT67F5652 датащи(PDF) 87 Page - Holtek Semiconductor Inc |
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HT67F5652 датащи(HTML) 87 Page - Holtek Semiconductor Inc |
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87 / 224 page ![]() Rev. 1.00 8� De�e��e� 0�� �01� Rev. 1.00 8� De�e��e� 0�� �01� HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU Timer/Counter Mode Toselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively. TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputMode generatingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutput pinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatch OutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode, thepincanbeusedasanormalI/Opinorotherpin-sharedfunction. PWM Output Mode Toselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively. ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotor control,heatingcontrol,illuminationcontroletc.Byprovidingasignaloffixedfrequencybut ofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwith varyingequivalentDCRMSvalues. AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgenerated waveformisextremelyflexible.InthePWMmode,theTnCCLRbithasnoeffectonthePWM operation.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,one registerisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,while theotheroneisusedtocontrolthedutycycle.Whichregisterisusedtocontroleitherfrequency ordutycycleisdeterminedusingtheTnDPXbitintheTMnC1register.ThePWMwaveform frequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters. Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematch occursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedto selecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedto enablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitis usedtoreversethepolarityofthePWMoutputwaveform. CTM, PWM Output Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Pe�iod 1�8 �5� 384 51� �40 ��8 89� 10�4 Duty CCRA IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128, TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%. IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthe PWMoutputdutyis100%. CTM, PWM Output Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Pe�iod CCRA Duty 1�8 �5� 384 51� �40 ��8 89� 10�4 ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeTMclock whilethePWMdutycycleisdefinedbytheCCRPregistervalue. |
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