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VSC8113 датащи(PDF) 12 Page - Vitesse Semiconductor Corporation

номер детали VSC8113
подробное описание детали  ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
PDF  28 Pages
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производитель  VITESSE [Vitesse Semiconductor Corporation]
домашняя страница  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation

VSC8113 датащи(HTML) 12 Page - Vitesse Semiconductor Corporation

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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8113
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 12
© VITESSE SEMICONDUCTOR CORPORATION
G52154-0, Rev 4.2
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
3/19/99
Table 7: Receive Data Output Timing Table
(STS-3 Operation)
Figure 11: Transmit High Speed Data Timing Diagram
Table 8: Transmit High Speed Data Timing Table
(STS-12 Operation)
Table 9: Transmit High Speed Data Timing Table
(STS-3 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLKIN
Receive clock period
-
6.43
-
ns
TRXLSCKT
Receive data output byte clock period
-
51.44
-
ns
TRXVALID
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
22
-
-
ns
TPW
Pulse width of frame detection pulse FP
-
51.44
-
ns
Parameter
Description
Min
Typ
Max
Units
TTXCLK
Transmit clock period
-
1.608
-
ns
TSKEW
Skew between the falling edge of TXCLKOUT+ and
valid data on TXDATAOUT
--
250
ps
Parameter
Description
Min
Typ
Max
Units
TTXCLK
Transmit clock period
-
6.43
-
ns
TSKEW
Skew between the falling edge of TXCLKOUT+ and
valid data on TXDATAOUT
--
250
ps
TTXCLK
TSKEW TSKEW
TXCLKOUT-
TXCLKOUT+
TXDATAOUT+
TXDATAOUT-



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