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VSC8113 датащи(PDF) 10 Page - Vitesse Semiconductor Corporation |
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VSC8113 датащи(HTML) 10 Page - Vitesse Semiconductor Corporation |
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10 / 28 page ![]() VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Page 10 © VITESSE SEMICONDUCTOR CORPORATION G52154-0, Rev 4.2 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 3/19/99 AC Timing Characteristics Figure 8: Receive High Speed Data Input Timing Diagram Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation) Table 3: Receive High Speed Data Input Timing Table (STS-3 Operation) Figure 9: Transmit Data Input Timing Diagram Parameter Description Min Typ Max Units TRXCLK Receive clock period - 1.608 - ns TRXSU Serial data setup time with respect to RXCLKIN 250 - - ps TRXH Serial data hold time with respect to RXCLKIN 250 - - ps Parameter Description Min Typ Max Units TRXCLK Receive clock period - 6.43 - ns TRXSU Serial data setup time with respect to RXCLKIN 1.5 - - ns TRXH Serial data hold time with respect to RXCLKIN 1.5 - - ns TRXCLK TRXSU TRXH RXCLKIN+ RXCLKIN- RXDATAIN+ RXDATAIN- TPROP TCLKIN TINSU TINH TXLSCKOUT TXLSCKIN TXIN [7:0] |
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