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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

87 of 142

parallel with LDOx_EN, the supply enable is deferred until the sequencer is processing the related

ID. The previous output voltage and enable state will be kept unchanged until the sequencer

processes the related time slot/ID during powering down (ignoring any assertions of VLDOx_GO

while LDOx_CONF is high).

Before wakeup from POWERDOWN mode (processing time slots from domain SYSTEM) the

sequencer will reset the LDOx_CONF bits and, if enabled via setting OTPREAD_EN, configure all

regulators with their default voltage values from OTP. The regulators can also be

enabled/disabled/configured via the power manager and HS-2-wire interface when the DA9021/22 is

in the ACTIVE state. Voltage transitions on LDOs including DVC will always be ramped.

NOTE

Powering down to RESET mode will automatically disable all regulators except for LDO1.

LDO 3 includes dynamic DVC control to enable power savings on peripheral domains:

● The output voltage is programmable over the power manager bus in 25 mV steps.

● The output voltage ramp step size is 6.25 mV/µs while slewing. If the feedback signal is

configured to be READY this line is asserted while slewing.

The DVC control is handled by the following registers:

● Output voltage setting register VLDO3 to configure the new target voltage.

● Activate bit VLDO3_GO will implement the changes on the LDO output (also used from the

sequencer for deferred voltage changes). After being started DA9021/22 will block (not accept

any re-programming of) the related voltage setting registers until slewing has been finished.

If selected the READY signal will be asserted during ramping.

LDO9 includes an optional hardware enable/disable via GPIO12 by selecting the GPI feature with

debouncing off. After detecting an E_GPI1, E_GPI2 or E_GPI12 event DA9021/22 will configure

LDO4_EN, LDO5_EN or LDO9_EN by the status of GPI1, GPI2 or GPI9 and the event bit E_GPI1,

E_GPI2 or E_GPI12 is automatically cleared. A parallel write access to LDO4_EN, LDO5_EN or

LD09_EN from the control interfaces or the power sequencer is delayed and will later override the

hardware configuration.

NOTE

It is recommended to assert the IRQ mask bit of GPIOs, which are configured for LDO hardware control, to

prevent the host being disturbed by IRQ strobes from the automatically cleared events.

Disabling regulators LDO1, 2 and 5 can switch off their pull down resistor, which is required for usage

in parallel to an alternate supply.

17.1 DA9021/22 core regulator LDOCORE

The LDOCORE will be used for running the DA9021/22 internal RTC module, internal state machine,

GPIO pins with comparators, bias, reference, GPADC, OTP and power manager registers. It is

supplied by the battery switch either from an external supply or VBAT.

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